Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-29
2003-05-13
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S301000
Reexamination Certificate
active
06563157
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-197795, filed Jun. 30, 2000, and No. 2001-175616, filed Jun. 11, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device having a rigid capacitor structure and a method for fabricating the same and more particularly to the structure of cell capacitors and fuse capacitors of a semiconductor memory device.
The development of the fine patterning technique of recent semiconductor devices is significant. Particularly, the fine patterning technique for DRAMs (Dynamic Random Access Memories) is increasingly developed. Therefore, the following subjects become important.
(1) How to form capacitors having sufficiently large capacitances in a limited area which becomes smaller as the area occupied by the memory cells becomes smaller.
(2) How to maintain the manufacturing yield to the same degree as the former generation with the progress of generations of integration.
The subject (1) can be coped with by using a cylinder structure for a cell capacitor, for example. The cylinder structure is one type of stacked capacitor and attains a large surface area while suppressing the occupied area by 3-dimensionally forming a cylindrical capacitor.
Further, as the technique for solving the subject (2), much attention is paid to the redundancy technique. The technique is attained by previously forming fuse elements in the semiconductor device in order to compensate for semiconductor elements which become partly defective. If the semiconductor element becomes defective, a fuse element corresponding to the defective portion is cut off to replace the defective semiconductor element by a spare semiconductor element, thus enhancing the manufacturing yield as a whole chip.
As the fuse elements, laser fuses in which information corresponding to the defective portion is written by fusing (laser-blowing) a metal interconnection layer by application of laser have been widely used. However, in recent years, electrical fuses for electrically cutting off or short-circuiting fuse elements have received much attention. As one type of the electrical fuse, an anti-fuse using the capacitor structure is provided. In the anti-fuse, information is written by applying high voltage to the fuse structure (fuse capacitor) to break down the insulating film and electrically short-circuiting the fuse capacitor. In the DRAM, the anti-fuse starts to be used in the redundancy technique for replacing the defective memory cell by a redundancy memory cell. Generally, the anti-fuse is formed by the same process as that for forming the cell capacitor structure.
The conventional DRAM structure is explained with reference to FIG.
1
.
FIG. 1
is a partial cross sectional view showing a DRAM using double-surface-cylinder type stacked capacitors.
As shown in
FIG. 1
, element isolation regions
11
are formed in a memory cell array area A
1
and peripheral area A
2
in a silicon substrate
10
and a gate insulating film
12
is formed on the silicon substrate
10
. The “memory cell array area” indicates an area in which memory cells of a DRAM are formed and the “peripheral area” indicates an area in which anti-fuses are formed. Gate electrodes
13
are formed on the gate insulating film
12
and MOS transistors are formed by selectively forming impurity diffused layers (not shown) functioning as a drain region and source regions in the silicon substrate
10
. The MOS transistors are used as cell transistors in the memory cell array area A
1
. Further, an interlayer insulating film
15
for covering the MOS transistors and a silicon oxide (SiO
2
) film
16
are sequentially formed on the gate insulating film
12
. Bit lines
17
connected to corresponding drain regions of the cell transistors in areas (not shown) are formed in the interlayer insulating film
15
of the memory cell array area A
1
and interconnection layers
17
connected to corresponding drain regions of the MOS transistors are formed in the peripheral area A
2
. Further, contact plugs
18
connected to the source regions of the cell transistors in the memory cell array area A
1
and the MOS transistors in the peripheral id area A
2
are formed in the interlayer insulating film
15
and silicon oxide film
16
. Then, double-surface-cylinder type capacitor lower electrodes
20
are formed on the silicon oxide film
16
so as to be connected to corresponding contact plugs
18
. An interlayer insulating film
22
is formed in an area on the silicon oxide film
16
in which no capacitor lower electrode
20
is formed. Capacitor insulating films
24
are respectively formed on the capacitor lower electrodes
20
. Capacitor upper electrodes
25
are formed on the capacitor insulating films
24
to respectively form cell capacitors and fuse capacitors in the memory cell array area A
1
and peripheral area A
2
. Further, an interlayer insulating film
27
is formed on the capacitors and a metal interconnection layer
29
is formed on the interlayer insulating film
27
to form a DRAM.
FIG. 2A
is a plane pattern of the capacitors of the above DRAM. In this example, a case wherein the DRAM is a 256-Mbit DRAM designed according to the 0.13 &mgr;m rule is shown.
As shown in
FIG. 2A
, cell capacitors
61
formed on an interlayer insulating film
60
are arranged at an interval of approx. 0.52 &mgr;m in the bit line direction and at an interval of approx. 0.26 &mgr;m in the word line direction. On the other hand, fuse capacitors
62
are arranged at an interval of approx. 1 &mgr;m and are generally arranged at an interval larger than at least twice the interval of the cell capacitors
61
. Thus, the cell capacitors in the memory cell array area A
1
are arranged in a large-scale array form and the fuse capacitors in the peripheral area A
2
are arranged in a small scale configuration of single bit to several bits in many cases. This is because the plate electrodes (upper electrodes) of the cell capacitors
61
are commonly connected, but all of the plate electrodes of the fuse capacitors
62
must be independently connected. Further, this is because high voltage for breaking down the fuse capacitors is applied to interconnections connected to the plate electrodes of the fuse capacitors, and therefore, it becomes necessary to use metal interconnections with large width.
With the above double-surface-cylinder type capacitor, since the bottom surface, inner peripheral surface and outer peripheral surface of the cylinder can be used as an electrode surface, the capacitance of the capacitor can be made large.
As a material of the capacitor insulating film of the conventional cell capacitor and fuse capacitor, a silicon oxide film is used. Further, a polysilicon film is used as a material of the capacitor electrode and an HSG (Hemi-Spherical Grained) silicon film is used to attain a larger surface area.
In recent years, attempts have been made to increase the capacitance of the capacitor by using a high-dielectric-constant material, for example, a tantalum oxide (Ta
2
O
5
) film having a larger dielectric constant in comparison with the silicon oxide film to form the capacitor insulating film. It is known that an element such as ruthenium in the platinum group is preferably used as a material of the capacitor electrode if the high-dielectric-constant material is used to form the capacitor insulating film.
However, elements belonging to the platinum group have poor adhesion with respect to a silicon oxide film generally used as an interlayer insulating film. Therefore, it is difficult to deposit and form a capacitor lower electrode by use of the platinum group element. Further, since the capacitor lower electrode is stripped from the peripheral interlayer insulating film after forming the capacitor lower electrode, the structure becomes fragile and the cylinder falls in some cases. In addition, a contact portion between the contact
Banner & Witcoff , Ltd.
Huynh Yennhu B.
Jr. Carl Whitehead
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