Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-31
2003-09-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000
Reexamination Certificate
active
06613633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a high power semiconductor device and a fabrication method thereof in which a junction breakdown voltage is increased and a snap-back characteristic is improved.
2. Description of the Conventional Art
An integrated circuit combining a control function and a driving function into one chip is called a smart power device. An output terminal of the smart power device is formed with a high power transistor that is operated at high voltages, such as between 15-80V. The logic operations are performed through normal transistors operating at a low voltage such as 5V. The smart power devices are mainly used to drive a display unit such as an LCD (liquid crystal display) or a HDTV (high definition TV).
The high voltage transistor of the smart power device is fabricated by employing a technique where a relatively lightly doped drift region is formed and a heavily doped drain region of the transistor is formed in the drift region. Also field oxide layers are formed above the device's substrate, including above the drift region, to define active regions.
In this technique, it is desirable that the field oxide layer formed above the drift region be spaced apart from an interface between the drift and drain regions, i.e. apart from a drain/drift junction, to increase the breakdown voltage of the device. It is also desirable to increase the snap-back voltage at the junction of the field oxide layer and at an edge of a gate electrode.
A high voltage transistor of a conventional smart power device will be described with references to
FIGS. 1 and 2
. Same reference numerals denote same elements in these figures.
FIG. 1
is a plan view of the high voltage transistor, and
FIG. 2
is a longitudinal-sectional view of the transistor taken along line of II—II of FIG.
1
.
As shown in
FIGS. 1 and 2
, an n-type well
110
is formed in a p-type semiconductor substrate
100
, and p
−
-type drift region
104
is formed in the n-type well
110
. The drift region
104
has a lower concentration of impurities than source/drain regions of the high voltage transistor (described below). The drift region
104
serves as a buffer layer, when a high electric field is applied to the drain region, to prevent junction breakdown and hot carriers from occurring.
A plurality of field oxide layers
101
are formed on the p-type semiconductor substrate
100
, the n-type well
110
, and the p-type drift region
104
.
Gate electrodes
102
are formed covering a predetermined portion of the n-type well
110
and the field oxide layers
101
. Note that an end portion of the gate electrode
102
toward a center of the drift region
104
is placed on an upper surface of the field oxide layer
101
. This prevents the field oxide layer from being destroyed due to a strong electric field formed at the end portion of the gate electrode
102
. The structure also increases the junction breakdown voltage as well.
Heavily doped p
+
-type source and drain regions
103
a
and
103
b
are formed inside the n-type well
110
and the drift region
104
, respectively. The source region
103
a
is formed adjacent to an end portion of the gate electrode
102
away from the center of the drift region
104
. The drain region
103
b
is formed adjacent to an edge of the field oxide layer
101
near the center of the drift region
104
. As noted above, the impurity concentration is much higher for the source and drain regions relative to the drift region
104
.
An insulation layer
106
, excluding the contact regions over the source and drain regions
103
a
and
103
b
, covers the entire structure including the field oxide layers
101
. The insulation layer
106
covers a portion of the drain region
103
b
to disperse the high electric field formed when voltage is applied to the drain region.
A source electrode
105
a
and a drain electrode
105
b
are formed and connected to the source and drain regions
103
a
and
103
b
, respectively, as shown.
However, the conventional smart power device described above has at least the following disadvantages. First, a high electric field is formed at the junction where the drift region and the n-well region meet (A in FIG.
1
). High electric field is also formed where at the interface where the field oxide layer
101
and the gate electrode
102
meet (B in FIG.
2
). These electric fields are not sufficiently dispersed in this construction. Second, the field oxide layer
101
is directly adjacent to the drain region
103
b
(C in FIG.
2
). In this instance, a junction profile is very steep resulting in a low breakdown voltage.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a high voltage transistor for a smart power device having a high breakdown voltage in which heavily doped source and drain regions do not directly contact an edge of a field oxide layer, and a fabricating method thereof.
Another object of the present invention is to provide a high voltage transistor for a smart power device having a high breakdown voltage in which a field plate is formed to disperse high electric field, generated when voltage is applied to source and drain regions of the device, to further increase breakdown voltage and improve reliability, and a fabrication method thereof.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, a high voltage transistor for a smart power device includes: a well of first conductivity formed in a substrate of second conductivity; a drift region of the second conductivity formed in the well; a source region of the second conductivity formed in the well between a substrate/well junction and a well/drift region junction, the source region having relatively higher concentration of dopants relative to the drift region; a drain region of the second conductivity formed in the drift region, the drain region having relatively higher concentration of dopants relative to the drift region; and a field oxide layer formed on the drift region such that an edge of the field oxide layer is spaced apart from the drain region by a predetermined distance. The high voltage transistor further includes a conductive field plate formed above the field oxide layer such that a portion of the field plate extends beyond the field oxide layer towards the drain region.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, a method to fabricate a high voltage transistor of a smart power device includes: forming a well of first conductivity in a substrate of second conductivity; forming a drift region of the second conductivity in the well; forming a source region of the second conductivity in the well between a substrate/well junction and a well/drift region junction, the source region having relatively higher concentration of dopants relative to the drift region; forming a drain region of the second conductivity in the drift region, the drain region having relatively higher concentration of dopants relative to the drift region; and forming a field oxide layer formed on the drift region such that an edge of the field oxide layer is spaced apart from the drain region by a predetermined distance. The method further includes forming conductive field plate above the field oxide layer such that a portion of the field plate extends beyond the field oxide layer towards the drain region.
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Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Niebling John F.
Roman Angel
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