Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-15
2003-07-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000
Reexamination Certificate
active
06596575
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device, and more particularly, to a semiconductor device having an isolation region of high breakdown voltage to separate a low breakdown voltage element region, and relates to a manufacturing process thereof. The present invention is particularly useful for a semiconductor device which enhances the breakdown voltage of the isolation region without impairing the characteristics of the elements in the low breakdown element region.
2. Description of the Prior Art
FIG. 12
shows a sectional view of a conventional semiconductor device including a high breakdown voltage isolation region
16
and the low breakdown voltage element region
17
. The conventional semiconductor device comprises a P− semiconductor substrate
1
, an n+ buried diffusion region
2
, an n− epitaxial layer
3
, a P− diffusion region
4
, a p+ diffusion region
5
, an n+ diffusion region
6
, a p+ diffusion region
7
, an n+ diffusion region
8
, a polysilicon electrode
9
, an electrode
10
and a silicon oxide film
11
. The n− epitaxial layer
3
is formed to have a higher impurity concentration than the P− substrate
1
, and the P− diffusion region
4
is formed to have a higher impurity concentration than the n− epitaxial layer
3
. Further, the P+ diffusion region
5
is formed to reach the substrate
1
.
The high breakdown voltage isolation region
16
functions to isolate a high voltage from a high-voltage region, typically located to the right of region
16
(not shown in FIG.
12
). However, high breakdown voltage elements sometimes may be integrally formed in the isolation region
16
. The low breakdown voltage element region
17
is integrally formed with low breakdown voltage elements
18
. Typically, the low breakdown voltage elements
18
include complementary metal oxide semiconductor (CMOS, shown in
FIG. 12
) and bipolar (BIP) elements, while high breakdown voltage elements in the isolation region
16
include elements utilizing a “Resurf” technology, (e.g., U.S. Pat. No. 4,292,642).
A problem with the above-described conventional configuration lies in that, when the resurf technology is employed to obtain high breakdown voltage, the product of thickness of the epitaxial layer
3
(unit: cm) and its impurity concentration (unit: cm
−3
) must be 9.0×10
11
(unit: cm
−2
) or less. When the high breakdown voltage isolation region
16
and the low breakdown voltage element region
17
are simultaneously formed within the range of thickness of the epitaxial layer
3
under such a restriction, the characteristics of the low breakdown voltage element
18
may be affected adversely.
FIG. 13
shows a correlation between a breakdown voltage of the high breakdown voltage isolation region
16
and of the low breakdown voltage element
18
of the conventional structure, and the thickness of the epitaxial layer
3
. The abscissa (i.e., X-axis) represents the thickness of the epitaxial layer
3
, and the ordinate (i.e., Y-axis) represents a magnitude of low and high breakdown voltage. As seen from
FIG. 13
, the thickness of the epitaxial layer
13
should be thinned to some degree to fully satisfy the characteristics of the high breakdown voltage isolation region or the high breakdown voltage element. Conversely, a second set of curves in
FIG. 13
shows epitaxial layer
3
should be thickened to some degree to assure the characteristics of the low breakdown voltage element. These conflicting breakdown relationships may cause a problem in that, when the thickness of the epitaxial layer
3
is thinned to fully satisfy the characteristics of the high breakdown voltage isolation region or the high breakdown voltage element, the P− diffusion region
4
, which becomes a P− back gate layer of an n-channel MOS transistor (nch MOS), will experience punch-through and thus lowering the breakdown voltage of the nch MOS. Thus, it is necessary to thicken the epitaxial layer
3
to some degree to satisfy the characteristics of the low breakdown voltage element.
Consequently, the thickness of the epitaxial layer
3
should be controlled within a very narrow range because it is necessary in the low breakdown voltage element region
17
to assure the thickness of the effective epitaxial layer
3
so not to adversely affect a characteristic of element
18
, excluding the “floating up” caused by n+ buried diffusion region
2
in the high breakdown voltage isolation region
16
, and to maintain sufficient thickness to exhibit the resurf effect. Thus, in the conventional semiconductor device including a high breakdown voltage isolation region and a low breakdown voltage element region, it is difficult to obtain a high breakdown voltage isolation region with sufficient breakdown voltage isolation, and concurrently not to impair the characteristics of the low breakdown voltage element
18
.
SUMMARY OF THE INVENTION
Accordingly, one object of this invention is to provide a novel device and process for manufacturing the device that overcomes the above-mentioned limitation of existing devices and manufacturing processes.
It is a further object of the invention to provide a semiconductor device including a high breakdown voltage isolation region and a low breakdown voltage element region, the high breakdown voltage isolation region having sufficient high breakdown voltage isolation, but not impairing the characteristics of a low breakdown voltage element in the low breakdown voltage element region, and to provide a manufacturing process therefor.
To accomplish the foregoing and other objects, and in accordance with the purposes of the present invention, a semiconductor device is provided in which a buried diffusion region of a second conductivity type (preferably, n+ type) is formed on a part of a semiconductor substrate of a first conductivity type (preferably, P− type). An epitaxial layer of the second conductivity type (preferably, n− type) is formed in contact with the semiconductor substrate and the buried diffusion region. A high breakdown voltage isolation region is formed in the epitaxial layer and contacts the semiconductor substrate. A low breakdown voltage element region is formed on the epitaxial layer. With this configuration, a thickness of the epitaxial layer formed in contact with the semiconductor substrate is lower than where the epitaxial layer is formed in contact with the buried diffusion region.
The above invention includes, although is not limited to, the following three ways to realize the invention.
Firstly, a semiconductor device comprising a semiconductor substrate of a first conductivity type (preferably, P− type); a buried diffusion region of a second conductivity type (preferably, n+ type) formed on a part of a primary surface of the semiconductor substrate; an epitaxial layer of the second conductivity type (preferably, n− type) formed in contact with the semiconductor substrate and the buried diffusion region, a primary surface of a portion of the epitaxial layer that is in contact with the semiconductor substrate being formed with an oxide film thereon, the oxide film being then removed therefrom; a high breakdown voltage isolation region formed on the epitaxial layer from which the oxide film is removed; and a low breakdown voltage element formed on a portion of the epitaxial layer which contacts the buried diffusion region.
Secondly, a semiconductor device comprising a semiconductor substrate of a first conductivity type (preferably, P− type); a buried diffusion region of a second conductivity type (preferably, n+ type) formed on a part of a primary surface of the semiconductor substrate; an epitaxial layer of the second conductivity type (preferably, n− type) formed in contact with the semiconductor substrate and the buried diffusion region, a primary surface of the epitaxial layer where a portion of the epitaxial laye
Nagatani Tatsuhiko
Terashima Tomohide
Lattin Christopher
Mitsubishi Denki & Kabushiki Kaisha
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