Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-05-17
2003-01-07
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S757000, C714S763000
Reexamination Certificate
active
06505319
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-135351, filed May 17, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing circuit for recording information on a recording medium, such as a DVD-RAM, and an information recording apparatus.
Recently have been developed optical disks, such as a CD-R and DVD-RAM, as rewritable recording media. A recording system which uses those optical disks needs to record a vast amount of information at a high speed and accurately reproduce recorded information. To achieve the requirements, an error correcting code is recorded together with record data.
FIG. 1
shows a conventional signal processing circuit which is used to add the parity of such an error correcting code to record data. When receiving record data supplied externally, a reception circuit
1
temporarily writes the record data in a memory section
3
constituted of a RAM or the like via an arbiter
2
. A parity adding circuit
4
reads record data, written in the memory section
3
, adds the parity of an error correcting code to the record data and writes back the parity-added record data into the memory section
3
via the arbiter
2
.
A transmission circuit
5
reads the record data, added with a parity by the parity adding circuit
4
, from the memory section
3
and sends the record data to a head section for recording information on a recording medium. At this time, the record data is converted to a drive current for a semiconductor laser, incorporated in the head section, by a driver before it is supplied to the head section. The arbiter is a memory interface which arbitrates an access to the memory section
3
by the reception circuit
1
, the parity adding circuit
4
and the transmission circuit
5
.
FIG. 2
conceptually depicts a memory area in the memory section
3
. The memory area of the memory section
3
is separated into three storage areas A, B and C whose sizes are each set approximately equal to the size of one block of data (ECC data block) in which a row of error correcting codes (ECCS) is completed.
FIG. 3
exemplarily shows a receiving process for record data, a parity adding process and a transmitting process for record data being carried out while switching the three storage areas A, B and C shown in
FIG. 2
from one to another. As illustrated, when the storage area A, for example, is a location where record data is to be written in the receiving process, the record data that was written in the storage area C in the previous phase is subjected to parity addition, and the storage area B that is undergone parity addition in this previous phase is subjected to data transmission.
In the next phase, the storage area B undergoes the receiving process, the storage area A undergoes the parity adding process and the storage area C undergoes the transmitting process. As apparent from the above, the individual storage areas are switched from one process to another in cycles, phase by phase. Because this system can execute the receiving process, parity adding process and transmitting process in parallel, the processing speeds of the individual circuits need not be enhanced so much. The system however requires that the memory capacity of the memory section
3
should be at least triple the size of a ECC data block.
Because the conventional signal processing circuit which is used in adding the parity of an error correcting code to record data has three storage areas in a memory section for record data in order to perform a receiving process for record data, a parity adding process and a transmitting process for record data in parallel, enlargement of the circuit scale is inevitable.
One way (not a prior art) to reduce the circuit scale having been conceived by the inventor is to separate the memory section for record data, which has a memory capacity twice as large as the size of an ECC data block, into two storage areas and to permit one storage area to undergo a transmitting process of record data while the other storage area is subjected to a receiving process for record data and a parity adding process.
FIG. 4
exemplarily shows the execution of a receiving process for record data, a parity adding process and a transmitting process for record data by switching the two storage areas A and B of the memory section from one to the other. In this case, however, while the transmitting process for one block of record data is being carried out in one storage area, the parity adding process should be carried out in serial after the completion of the receiving process for one block of record data in the other storage area. This requires the improvement of the processing speeds of the reception circuit
1
and the parity adding circuit
4
shown in
FIG. 1
in order to avoid a wasteful wait time in the transmitting process. This demands a considerable amount of burden on the individual circuits and faster data transfer.
Accordingly, it is an object of the present invention to provide a signal processing circuit which is used in adding the parity of an error correcting code to record data, can improve the speed of processing record data without significantly increasing the circuit load, and can reduce the memory capacity of storage areas for record data.
It is another object of this invention to provide an information recording apparatus equipped with such a signal processing circuit.
BRIEF SUMMARY OF THE INVENTION
To achieve the above object, according to one aspect of this invention, there is provided a signal processing circuit comprising: reception section configured to receive record data; a memory section configured to store the record data received by the reception section; a parity adding section configured to add record data stored in the memory section with a parity based on an error correcting code in a unit of record data block; and a transmission section configured to transmit parity-added record data stored in the memory section; wherein the memory section has two storage areas each of which has a capacity for at least one record data block and which are alternately switched to a parity-added data storage area where record data added with the parity by the parity adding section is stored and a transmission area from which the parity-added record data is read and transmitted by the transmission section, the reception section is configured to receive the record data in an order matched with an order of rows of error correcting codes, and the parity adding section starts adding the parity to record data upon reception of record data for one row of error correcting codes.
According to another aspect of this invention, there is provided an information recording apparatus comprising a head section for recording information on a recording medium; a reception section configured to receive record data at a time of recording information on the recording medium; a memory section configured to store the record data received by the reception section; a parity adding section configured to add record data with a parity based on an error correcting in a unit of record data block; and a transmission section configured to transmit parity-added record data stored in the memory section, wherein the memory section has two storage areas each of which has a capacity for at least one block of the record data and which are alternately switched to a parity-added data storage area where record data added with the parity by the parity adding section is stored and a transmission area into which the parity-added record data is read and transmitted by the transmission section, and the parity adding section starts adding the parity to record data upon reception of record data for one row of error correcting codes.
This invention is designed paying attention to the fact that a process of adding the parity of an error correcting code, with respect to record data externally received in an o
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