Process to create robust contacts and interconnects

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S637000

Reexamination Certificate

active

06534394

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to semiconductor processing, and more specifically relates to a process to create robust contacts and interconnects.
2. Background Art
There are structures on a semiconductor wafer where a metal or other conductive film is deposited over a layer that has apertures in it. These apertures allow the metal to contact underlying structures. For example, a connection might be needed to connect a particular metal run, which is itself connected to a number of gates, to the metal film. A hole is made in an insulating film right above the metal run. When the metal film is deposited, there will be a good connection between the metal run and the metal film. The metal film may then be planarized, masked and etched, etc., to electrically connect the metal film to other devices that will control the gates.
Currently, some semiconductor processes can create relatively deep apertures. For example, “high aspect ratio vias” are connections between metal layers where the height of the hole is greater than the width of the hole. Such high aspect ratio structures can have heights that are six or more times larger than their widths.
To ensure that metal evenly covers the bases of these structures and properly lines them, ionized deposition processes have been used. Although not limited to use for these types of high aspect ratio structures, the ionized deposition process has the benefit of creating metal sputter flux with trajectories made to be more perpendicular to the surface of a semiconductor wafer. This helps cause the metal to go deep into the high aspect ratio structures.
Unfortunately, there are problems associated with ionized deposition processes. What is needed is a process that overcomes these problems and creates more robust contacts and interconnects.
DISCLOSURE OF THE INVENTION
The preferred embodiment of the present invention provides a method to create robust contacts and interconnects by depositing a thin layer of a first conductive material on a wafer through a non-ionized deposition process. The thin layer overlays the wafer and lines any apertures in the wafer. Deposition of a first conductive material is followed by depositing another thin layer of a second conductive material by an ionized deposition process. In this manner, the second conductive material overlays the first conductive material and additionally lines the wafer and any apertures in the wafer. Furthermore, if the apertures open to underlying areas, the conductive materials that line the apertures preferably create a conductive film that can form a plurality of contacts between the conductive film and the underlying areas.
One advantage of the present invention is that by following the method of the preferred embodiment, charge differentials due to non-uniform plasmas are not created across the wafer because the initial thin layer of a first conductive material is deposited through a non-ionized deposition process. Therefore, for example, transistor degradation or other device degradation will be prevented when the subsequent preferred step of ionized deposition of a second conductive material is carried out. Thus, the preferred method avoids charge differentials created by non-uniform plasmas, yet avoids a “center thick” deposition profile along the surface of the wafer. Specifically, the preferred method allows the use of non-uniform plasmas that enable sputtering to be done in an uneven “center thin” profile along the target, thereby allowing uniformity of deposition thickness to be provided on the surface of the wafer.
Another advantage of the method of the preferred embodiment is that metal interfaces created in aperture bases are not contaminated with oxide, FSG (fluorinated silica glass), SiLK (organic material sold by DOW), or other dielectric or interposed material, thereby eliminating high contact or via junction resistance.
Still another advantage of the method of the preferred embodiment is that it can augment and provide substantial improvements to the sequentially deposited tantalum nitride/tantalum (TaN/Ta) bilayer process.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.


REFERENCES:
patent: 4492620 (1985-01-01), Matsuo et al.
patent: 5830330 (1998-11-01), Lantsman
patent: 5849367 (1998-12-01), Dixit et al.
patent: 5902461 (1999-05-01), Xu et al.
patent: 5961793 (1999-10-01), Ngan
patent: 5962923 (1999-10-01), Xu et al.
patent: 6051114 (2000-04-01), Yao et al.
patent: 6218302 (2001-04-01), Braeckelmann et al.
patent: 6261946 (2001-07-01), Iacoponi et al.
patent: 6274483 (2001-08-01), Chang et al.
patent: 6342448 (2002-01-01), Lin et al.
patent: 6423636 (2002-07-01), Dordi et al.

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