Self burn-in circuit for semiconductor memory

Details Self burn-in circuit for semiconductor memory Self burn-in circuit for semiconductor memory

1996-01-19

2002-10-29

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189070

Reexamination Certificate

active

06473346

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self burn-in circuit for semiconductor memory, and in particular to an improved self burn-in circuit for a semiconductor memory capable of generating a control signal, an address, and a test data from the interior of a chip for a burn-in test operation when a certain self burn-in test condition is satisfied.
2. Description of the Conventional Art
Generally, as well known to those who skilled in the art, the burn-in test is referred to a process for testing chip by applying a certain level voltage higher than that of a normal voltage so that an initial error of chip can effectively checked for a relatively short time. However, in order to prevent the reliability decrease of the product in accordance with a fineness of chip and to implement a low voltage consumption, an internal power generator is provided, so that the device of the chip can be driven by voltage lower than an externally supplied voltage. The internal voltage generator has a characteristic of maintaining a constant level of voltage irrespective of variation of an externally supplied voltage in a normal operation interval so as to secure chip reliability and stable operation. Therefore, a certain voltage higher than that of the normal operation should be applied to the entire devices of the chip. Therefore, an externally supplied voltage enters a burn-in test interval beyond the normal operation interval, the internal voltage generator maintaining a constant voltage should generate voltage proportional to the variation of the externally supplied voltage. That is, in case that the level of the externally supplied voltage applied to the chip is beyond the normal operation interval and approaches a burn-in start voltage, the burn-in circuit detects the above-mentioned state and converts the operation state of the chip into a burn-in test mode. In addition, in case that the externally supplied voltage is converted into the normal operation state, the burn-in circuit acts as a role of converting the operation state of the chip into the normal operation mode.
As described above, the conventional burn-in circuit for testing a burn-in test is directed to detecting a start of the burn-in operation when an externally supplied voltage is increased up to a certain level by providing a burn-in detection unit and to performing a cell aging operation by receiving a test data so as to test the operation the cell for selecting a control signal and a cell array from the outside of the system.
However, the conventional burn-in circuit for a burn-in test has disadvantages in that in a state that the memory chip is connected to the burn-in test apparatus, since a control signal, an address and a test data outputted from the burn-in test apparatus is provided to the chip, the test board becomes complicated due to lines for receiving and transmitting signals, so that the number of chips available is limited, and the test process becomes complicated.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a self burn-in circuit for a semiconductor memory, which overcome the problems encountered in a conventional self burn-in circuit for a semiconductor memory.
It is another object of the present invention to provide an improved self burn-in circuit for a semiconductor memory capable of generating a control signal, an address, and a test data from the interior of a chip for a burn-in test operation when a certain self burn-in test condition is satisfied.
To achieve the above objects, there is provided a self burn-in circuit for a semiconductor memory, which includes a burn-in detector for generating a certain control signal, an address signal, and a test data for a burn-in test operation when a certain self burn-in test condition is achieved; and a memory array for performing a burn-in test operation when said test data is written on/read from a memory cell which is selected by said address signal in accordance with said control signal.


REFERENCES:
patent: 5321653 (1994-06-01), Suh et al.
patent: 5452253 (1995-09-01), Choi
patent: 5471429 (1995-11-01), Lee et al.
patent: 5537537 (1996-07-01), Fujikawa et al.

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