Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-11
2002-10-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S228000, C438S276000, C438S289000, C438S306000
Reexamination Certificate
active
06461921
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a field effect transistor such as a MOSFET or MISFET and a method of manufacturing the same and, more particularly, to a semiconductor device having an E (Enhancement) type or D (Depletion) type transistor and an I (Intrinsic) type transistor, and a method of manufacturing the same.
In the field of semiconductors, market demands for higher element densities within chips and low-cost LSIs (semiconductor devices) are still present even at present. Particularly, in semiconductor memories such as nonvolatile memories, an increase in memory capacity and a decrease in chip size by increasing the element density, and a reduction in manufacturing cost by simplifying the process are urgent subjects.
Conventional measures to decrease the chip size will be described by exemplifying a nonvolatile memory.
In a nonvolatile memory, a high voltage is used in a data write and erase. This high voltage is generally obtained by boosting an external power supply voltage using a booster circuit based on a charge pumping technique within an LSI (reference
1
: “Design for CMOS VLSI”, edited by Iizuka, Baifuukan, pp. 192-193).
The booster circuit must be constituted by a large-capacity capacitor element because it must generate a very high voltage. Increasing the capacity of the capacitor element generally means to increase the capacitor area, i.e., the capacitor element itself. Accordingly, the occupied area of the booster circuit on the chip increases, resulting in a large chip size and high cost.
To solve this problem, in the nonvolatile memory, the boosting efficiency is conventionally increased by constituting the booster circuit by a MOSFET having a threshold voltage as low as about 0.1V and a small back-gate bias effect, (which is to be referred to as an I (Intrinsic) type MOSFET).
An I type n-channel MOSFET can be formed on a p-type silicon substrate having an impurity concentration of about 2×10
16
cm
−3
because no threshold voltage control impurity is implanted in an element area (channel portion of the MOSFET) (reference
2
: S. M. Sze, “Semiconductor Device”, translated by Nanjitsu, Kawabe, and Hasegawa, Sangyotosho, pp. 220-221).
That is, since no threshold voltage control impurity is implanted in the channel portion, the I type MOSFET is different from a general E type MOSFET in which a threshold voltage control impurity is implanted in a channel portion. In addition, the I type MOSFET has a smaller back-gate bias effect than that of the E type MOSFET (reference
3
: “Foundation of MOS Integrated Circuit”, edited by Takeishi and Hara, Kindaikagakusha, pp. 12-13).
In this manner, constituting the booster circuit based on the charge pumping technique by the I type MOSFET contributes to a decrease in chip size because an increase in capacity of the capacitor element can be suppressed as low as possible in generating a high voltage.
In the field of semiconductors, the manufacturing cost must be reduced by simplifying the process (decreasing the number of steps) in order to achieve low-cost LSIs. Some conventional manufacturing methods will be described.
FIG. 33
is a sectional view of a semiconductor device formed by the first example of a conventional manufacturing process.
FIG. 34
is a flow chart briefly showing the main steps of this manufacturing process.
As shown in
FIG. 33
, this semiconductor device comprises an E type or D type n-channel MOSFET
110
a
formed using a p-type well layer
115
in a p-type silicon substrate
111
, and an I type MOSFET
110
b
formed using the ground of the p-type silicon substrate
111
. Each element is surrounded by grating-like field oxide films, i.e., element isolation films
119
. A p-type channel stopper diffusion layer
120
is formed immediately below each element isolation film
119
.
In the first example of the manufacturing process, a PEP (PhotoEtching Process), ion implantation, and thermal diffusion are performed in step S
11
to form the p-type well layer
115
. In step S
12
, a PEP, ion implantation, and LOCOS oxidation are performed to form the element isolation films
119
and the p-type channel stopper diffusion layers
120
. In step S
13
, a PEP and ion implantation are performed to implant an impurity for controlling the threshold voltage of the MOSFET
110
a
. In step S
14
, formation of the gate electrode and self-alignment ion implantation are performed to implant an impurity for forming source and drain layers. In step
515
, the impurity is activated by annealing to complete the source and drain layers.
This manufacturing process is characterized by the well diffusion process and the three PEPs. That is, since the well diffusion process is a long-time thermal diffusion process, ion implantation for the well layer
115
and ion implantation for threshold voltage control or a channel stopper cannot be simultaneously performed.
FIG. 35
is a sectional view of a semiconductor device formed by the second example of the conventional manufacturing process.
FIG. 36
is a flow chart briefly showing the main steps of this manufacturing process. The same reference numerals as in
FIG. 33
denote the same parts of the sectional structure in
FIG. 35
, and a description thereof will be omitted.
In the second example of the manufacturing process, a PEP and LOCOS oxidation are performed in step S
21
to form element isolation films
119
. In step S
22
, a PEP and ion implantation are performed to implant an impurity for forming p-type channel stopper diffusion layers
120
. In step S
23
, a PEP and ion implantation are performed to implant an impurity for controlling the threshold voltage of a MOSFET
110
a
and an impurity for forming a p-type well layer
115
. In step S
24
, formation of a gate electrode and self-alignment ion implantation are performed to implant an impurity for forming source and drain layers. In step
525
, the impurities are activated by annealing to complete the well layer
115
, the channel stopper diffusion layers
120
, and the source and drain layers.
FIGS. 37
to
42
are views sequentially showing the third example of the conventional manufacturing process as an improvement of the second example.
FIG. 43
is a flow chart briefly showing the main steps of this manufacturing process.
In the third example of the manufacturing process, as shown in
FIGS. 37 and 38
, a silicon oxide film
112
is formed on a p-type silicon substrate
111
by, e.g., thermal oxidation. A silicon nitride film
116
is formed on the silicon oxide film
112
by, e.g., LPCVD.
A resist pattern
117
is formed on the silicon nitride film
116
by a PEP (PhotoEtching Process). Using the resist pattern
117
as a mask, the silicon nitride film
116
is patterned by RIE (Reactive Ion Etching).
Using the resist pattern
117
as a mask, a p-type impurity (e.g., boron ions)
118
is ion-implanted in the silicon substrate
111
. Then, the resist pattern
117
is removed.
As shown in
FIG. 39
, LOCOS oxidation is performed using the silicon nitride film
116
as a mask to form field oxide films
119
having a film thickness of about 500 nm on the silicon substrate
111
. At the same time, p-type diffusion layers (channel stoppers)
120
are formed immediately below the field oxide films
119
. Thereafter, the silicon nitride film
116
is removed.
As shown in
FIGS. 40 and 41
, a resist pattern
121
is formed on the silicon oxide films
112
and the field oxide films
119
by a PEP. The resist pattern
121
has an opening above an element area where a general E type MOSFET is to be formed, and covers an element area where an I type MOSFET is to be formed.
Using the resist pattern
121
as a mask, a p-type impurity (e.g., boron ions)
128
is implanted to a deep portion in the silicon substrate
111
by high-energy ion implantation using a plurality of different acceleration energies of, e.g., about 400 keV and 300 keV.
Using the resist pattern
121
as a mask, a p-type impurity (e.g., boron ions)
129
for controlling the threshold voltage of
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Malsawma Lex H.
Smith Matthew
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