Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate
Reexamination Certificate
2001-02-07
2002-10-08
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
C438S607000, C438S931000, C438S778000
Reexamination Certificate
active
06461944
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the growth of semiconductor device crystal films. Specifically, the invention provides a method for growing arrays of cantilevered web structures on semiconductor wafers. In addition, the cantilevered web can be made step-free (i.e., atomically flat) for fabrication of wide bandgap semiconductor devices. The wide bandgap semiconductor devices find application in high power, high frequency, high temperature and/or high radiation environments, as well as use in optoelectronic devices such as semiconductor lasers and light-emitting diodes.
BACKGROUND OF THE INVENTION
Conventional semiconductors (such as silicon & GaAs) are unable to meet some of the increasing demands of the automobile and aerospace industries as they move to smarter and more electronic systems. New wide bandgap (WBG) materials are being developed to meet the diverse demands for more power at higher operating temperatures. Two of the most promising emerging wide bandgap semiconductors are silicon carbide (SiC) and Gallium Nitride (GaN). At over three electron volts, the bandgap of these materials is nearly three times as large as that of silicon. This advantage theoretically translates into very large improvements in power handling capabilities and higher operating temperatures that will enable revolutionary product improvements. Once material-related technology obstacles are overcome, SiC's properties are expected to dominate high power switching and harsh-environment electronics for manufacturing and engine control applications, while GaN will enable high power high frequency microwave systems at frequencies beyond 10 GHz. To date the best SiC devices to our knowledge are homojunction (i.e., wafer and device layers are all hexagonal SiC), while GaN devices are heterojunction (i.e., SiC or sapphire wafers with device layers of GaN, AlGaN, AlN, etc.) because production of bulk GaN wafers is not practical at the present time.
While great advances have been made in recent years, significant fundamental materials problems persist that severely hinder commercialization and beneficial system insertion of wide bandgap electronics. One of the most intransigent of these problems is the high structural defect (e.g., dislocation) density in SiC and GaN layers in which electronic devices are constructed. Another is the very rough surface structure of SiC (relative to silicon surfaces) which inhibits the performance and reliability of various device structures, especially SiC-based MOSFET's. (Silicon-based MOSFET's are the transistor of choice in greater than 95% of all semiconductor chips produced today). This rough surface of SiC also degrades the quality of GaN layers grown on SiC, which nevertheless still yields the most promising GaN/AlGaN devices reported to date.
A number of prior art processes have been developed that contribute somewhat to the solution of the problem of defects and the rough surfaces that are produced in current epitaxial film growth processes. However, each of these prior art processes has limitations and disadvantages.
Prior art processes having many advantages are described in U.S. Pat. Nos. 5,915,194 and 6,165,874. These processes can produce step-free (atomically-flat) surfaces on the top of arrays of small mesas (flat-topped, protruding regions on a semiconductor wafer) that are etched into the surface of commercially-produced SiC wafers. The disadvantage of this prior art process is that the area sizes of the step-free mesas are limited by the defect density (e.g., screw dislocations) in the SiC wafer as described in the technical article entitled “Growth of Step-Free Surfaces on Device Size SiC Mesas” of Powell and Neudeck et al published Sep. 4, 2000, in Applied Physics Letters, Volume 77, number 10, pages 1449 to 1451. For current typical commercial SiC wafers this places a practical maximum area mesa size for a step-free surface at about 200 &mgr;m×200 &mgr;m. There are many semiconductor devices, which are larger than this rendering inadequate the 200 &mgr;m×200 &mgr;m step-free areas for some important device applications. In particular, high current power devices typically require larger areas than 200 &mgr;m×200 &mgr;m.
Another prior art process is lateral epitaxial overgrowth (LEO) (also commonly referred to as ELO for extended lateral overgrowth) of semiconductor films used to produce films with reduced defect density that is described by the authors Davis et al., given in the proceedings of ICSCRM '99, Materials Science Forum, Vols. 338-342, pp. 1471-1476 and references therein, as well as U.S. Pat. No. 6,051,849 of Davis et al. An example of this reduced density is the ELO of GaN and AlN films on SiC and sapphire substrates; this includes the so called, known in the art, “pendeo-epitaxy” of GaN. A problem with these forms of ELO is that growth takes place in both vertical and lateral directions. Therefore, the material deposited to grow the prior art ELO film vertically necessarily reduces the lateral direction growth rate which is desired to be high to maximize the practical lateral extent of the overgrowth region. Also, the ELO process does not produce a step-free top surface. Also, the vertical growth above the original “seed” crystal surface disadvantageously contains a high density of defects. Finally, the region of coalescence of films grown from adjacent seed areas can be defective. Dislocation defects are described in the technical article of P. Venne'gue's, B. Beaumont, V. Bousquet, M. Vaille, and P. Gibart, entitled “Reduction Mechanisms for Defect Densities in GaN Using One or Two-Step Epitaxial Lateral Overgrowth Methods,” published in J. Appl. Phys., vol. 87, no. 9, pp. 4175-4181, 2000. The technical article of P. Venne'gue's gives examples of dislocation defects, for both of those formed above the original seed and for those formed in the region of coalescence, that result from the present ELO processes. In order to achieve useful device size (area) with present ELO process, coalescence (and resulting imperfections) is required. It is desired that a process for growing large-area devices be provided that does not suffer the drawbacks of the prior art.
It is well known that dislocation defects in III-nitride layers are known to degrade the performance and reliability of III-nitride electronic devices. Some examples of dislocation-related degradation of lasers and other devices are described in the technical article of S. J. Pearton, J. C. Zolper, R. J. Shul, and F. Ren, entitled “GaN: Processing, Defects, and Devices,” published in J. Appl. Phys., vol. 86, no. 1, pp. 1-78, 1999. Further examples are described in the references referred to in the technical article of S. J. Pearton et al.
OBJECTS OF THE INVENTION
It is a primary object of the present invention to provide a method for growing arrays of large-area-device-size films having step-free surfaces in excess of about 200 &mgr;m×200 &mgr;m (i.e., the practical area limitation imposed by screw dislocations in SiC wafers).
It is another object of the present invention to produce a large-area step-free surface that can be used for subsequent heteroepitaxial growth of improved quality 3C-SiC, AlN, GaN, and other semiconductor materials with few defects.
In addition, it is an object of the present invention to provide a method that uses lateral growth behavior of step-free SiC mesas as the basis for the formation of cantilevers at the top edges of the mesas. Hence, after the top surface becomes step-free, there is only lateral growth (i.e., no vertical growth as in other prior art processes).
Moreover, it is an object of the present invention to provide a method that yields larger areas of atomically flat surfaces larger than the prior art 200 &mgr;m×200 &mgr;m limitation imposed by substrate defects (e.g., screw dislocations) for fabrication of electrical and optical devices.
Furthermore, it is an object of the present invention to provide a method that yields lateral overgrowth that terminates vertic
Neudeck Philip G.
Powell J. Anthony
Elms Richard
Luhrs Michael K.
Stone Kent N.
The United States of America as represented by the Administrator
LandOfFree
Methods for growth of relatively large step-free SiC crystal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for growth of relatively large step-free SiC crystal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for growth of relatively large step-free SiC crystal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2999444