Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-04-17
2002-12-31
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C714S745000
Reexamination Certificate
active
06502215
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to electronic devices, and more particularly to memory devices and methods of testing such devices.
BACKGROUND OF THE INVENTION
Computer designers desire fast and reliable memory devices that will allow them to design fast and reliable computers. Manufacturers of memory devices, such as random access semiconductor memories, must test a full range of functionality and timing characteristics of the memory devices in order to provide a reliable product to their customers. Because each memory cell or bit of the memory device must be tested, the time and equipment necessary for testing memory devices of ever increasing cell number and density represents a significant portion of the overall manufacturing cost of such devices. Any reduction in the time to test each unit will reduce manufacturing costs.
Manufacturers of memory devices increasingly automate the testing procedure in order to save on testing time and cost. Automated testing is most easily accomplished after the memory device has been packaged as a semiconductor chip, because the chip can be inserted into a test socket. Automated testing circuitry then applies predetermined voltages and signals to the chip, writes test data patterns to the memory, reads data, and analyzes the results to detect memory speed, timing, failures, etc. The more chips that can be tested simultaneously, the greater testing time savings per chip.
Still more time can be saved if testing is performed simultaneously with other end-step manufacturing processes. For example, many manufacturers use a “burn-in” process to screen out devices that are likely to fail at an unacceptably early time following manufacture. During the burn-in process, memory chips are subject to elevated temperatures and voltages which then accelerate failures in any inherently weaker chips. The ability to automatedly and simultaneously test multiple chips during the burn-in process, rather than afterwards, saves time and reduces manufacturing cost.
While much of cell-to-cell defect and functionality testing can be accomplished during the bum-in process, speed testing memory chips has not been performed during burn-in. This is because speed testing today's increasingly fast memory devices requires highly precise generation of timing signals and precise measurement of memory device response thereto. Currently available speed testers do not perform well in the extreme environment of the bum-in process. Also, current speed testing equipment tests very few memory chips at a time, because capacitive loading and signal delay effects must be minimized. Thus, current speed testing equipment and methods add disproportionately to the testing time and manufacturing cost per chip.
Unsuccessful attempts have been made to address the disproportionate time and cost of speed testing by fabricating circuitry, on the chip to be tested, capable of providing at least some of the test functions usually provided by external speed testing equipment. For example, a predetermined data pattern is first written to the memory device and then accessed during a read cycle. Comparator circuits fabricated on-chip compare the read data to the predetermined data pattern and indicate whether the data accessed matches the expected pattern. For purposes of speed testing, these comparator circuits must perform the comparison function at particular determined times to indicate whether the expected data has been successfully accessed at those particular times. On-chip delay circuits have been constructed to provide the precise clocking signals necessary to trigger the function of the comparator circuits.
Speed testing is performed to determine in which of a number of determined speed grades a particular memory device belongs. Because of manufacturing process tolerance and variations, one memory device of a particular design may be faster than another memory device of the very same design. Because the on-chip delay circuits are themselves subject to the same process variations as the rest of the circuitry on the chip, these delay circuits cannot reliably be used to measure the effects of those variations.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor memory device is provided that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data. The memory device also includes a control circuit receiving a system clock signal and controlling data transfer operations between the array of memory cells and an external data bus. The memory device further includes a test circuit receiving the system clock signal and coupled to an internal data bus. When operated in the speed test mode, the control circuit provides a test enable signal to the test circuit. A predetermined data pattern is written to one or more cells and subsequently accessed during a read cycle. The enabled test circuit compares the contents of the internal data bus to the predetermined data pattern at a time referenced to the system clock signal. The test circuit then produces a signal that places the external data bus in one of two states corresponding to whether a passed or failed comparison has occurred.
In a preferred embodiment, the test circuit includes a data pattern circuit that stores the predetermined data pattern and provides this pattern to a data compare circuit. The data compare circuit receives the clock signal and the test enable signal, and compares the contents of the internal data bus to the predetermined data pattern at a time referenced to the clock signal. In the event of a failed comparison, the data compare circuit produces a signal that disables an output circuit coupling the internal data bus and the external data bus.
REFERENCES:
patent: 4194432 (1980-03-01), Conway et al.
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4553225 (1985-11-01), Ohe
patent: 4958345 (1990-09-01), Fujisaki
patent: 5072137 (1991-12-01), Slemmer
patent: 5075892 (1991-12-01), Choy
patent: 5301155 (1994-04-01), Wada et al.
patent: 5309446 (1994-05-01), Cline et al.
patent: 5430680 (1995-07-01), Parris
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5457696 (1995-10-01), Mori
patent: 5483175 (1996-01-01), Ahmad et al.
patent: 5550784 (1996-08-01), Takai
patent: 5568437 (1996-10-01), Jamal
patent: 5661729 (1997-08-01), Miyazaki et al.
patent: 5692165 (1997-11-01), Jeddeloh et al.
Pinney David L.
Raad George B.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Ton David
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