Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-03
2002-10-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000
Reexamination Certificate
active
06458643
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a MOS device with an ultra-shallow junction (USJ) extension region.
2. Description of the Prior Art
In a very large scale integration (VLSI) process, ion implantation in a doping process is the most common method used to control the quantity and distribution of dopants in a semiconductor wafer and decrease thermal budget. As dimensions of electrical elements become smaller, improvement of ion implantation focuses on fabrication of a shallow junction functioning as a source extension or a drain extension of a metal-oxide semiconductor (MOS) transistor with dimensions in the range of microns.
Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are schematic diagrams of a method of forming a MOS device with a shallow junction extension regionaccording to the prior art. As shown in
FIG. 1
, a semiconductor substrate
10
is provided. A dielectric layer
12
, such as a silicon dioxide layer, is positioned on the surface of the semiconductor substrate
10
functioning as a gate oxide layer. Subsequently, a polysilicon layer (not shown) is deposited on the surface of the semiconductor substrate
10
followed by the use of a photolithographic and etching process to remove a portion of the polysilicon layer to form a gate
14
. A chemical vapor deposition (CVD) is then performed to deposit a dielectric layer
16
of silicon nitride with a thickness of 500 to 2000 angstroms (Å) on the surface of the semiconductor substrate
10
.
As shown in
FIG. 2
, a photoresist layer
18
is formed on the surface of the dielectric layer
16
. Then, a planarization process is used to etch back a portion of the photoresist layer
18
down to the surface of the dielectric layer
16
atop the gate
14
. As a result, the top surface of the remaining photoresist layer
18
on either side of the gate
14
aligns approximately with the top of the gate
14
. As shown in
FIG. 3
, using the photoresist layer
18
as a mask layer, a dry etching process is performed to remove the dielectric layer
16
adjacent to the gate
14
. After that, a first ion implantation process is performed to implant n-type dopants, such as arsenic ions, into both the gate
14
and the semiconductor substrate
10
not covered by the photoresist layer
18
with an implantation energy of approximately 70 KeV and an implantation dosage of approximately 1×10
13
/cm
2
. As a result, a pocket implant region
20
is formed within the semiconductor substrate
10
adjacent to the gate
14
.
As shown in
FIG. 4
, after the photoresist layer
18
and the dielectric layer
16
are removed, a second ion implantation process is performed using p-type dopants, such as boron ions with an implantation energy of about 2 to 3 KeV and an implantation dosage of about 1×10
15
/cm
2
, thus forming a source/drain extension doping region
22
within the semiconductor substrate
10
adjacent to the gate
14
. Then, a first rapid thermal annealing (RTA) is performed to activate both the pocket implant region
20
and the source/drain extension doping region
22
.
As shown in
FIG. 5
, a dielectric layer such as an oxide layer or a silicon nitride layer (not shown) is uniformly deposited on the surfaces of the gate
14
and the semiconductor substrate
10
. Thereafter, an anisotropic etching process is performed to etch back the dielectric layer as well as to form a spacer
24
by the remaining dielectric layer on either side of the gate
14
. Following this, a third ion implantation process is performed still using p-type dopants, such as boron, with an implantation energy of about 5 KeV and an implantation dosage of about 1×10
15
/cm
2
to form a source/drain doping region
26
within the semiconductor substrate
10
outside of the spacer
24
. Finally, a second RTA process is performed to activate the dopants within the source/drain doping region
26
to finish the fabrication of the MOS device with the shallow junction extension regions.
In order to achieve the SIA-roadmap standard of the junction depth (the junction depth in a 0.1-micron process should be in the range of 200 to 400 Å), a decrease in the implantation energy of ion beams is required. While decreasing the implantation energy, a short channel effect (SCE) is thus prevented as a result of the increase in the integration of the electrical elements. However, decreasing the implantation energy results in a decrease in the beam current, which inevitably slows down the implantation rate to incur time delay and higher cost. In addition, except for a normal thermal diffusion, the high-energy ions implanted within the pocket implant region
20
occur a transient enhanced diffusion (TED) during the first RTA process, thus ineffectively decreasing the junction depth.
SUMMARY OF INVENTION
It is therefore an objective of the present invention to provide a method of fabricating a MOS device with an ultra-shallow junction (USJ) extension region.
It is another objective of the present invention to provide a method of fabricating a MOS device with an ultra-shallow junction (USJ) extension region to reduce transient enhanced diffusion (TED) effects.
According to the claimed invention, a semiconductor substrate is provided with at least a gate formed on the semiconductor substrate. A first ion implantation process is performed to form a pocket implant region within the semiconductor substrate beneath the gate. After the first ion implantation process, a first rapid thermal annealing (RTA) process is immediately performed to reduce TED effects resulting from the first ion implantation process. Thereafter, a second implantation process is performed to form a source extension doping region and a drain extension doping region within the semiconductor substrate adjacent to the gate. A spacer is then formed on either side of the gate followed by a third ion implantation process to form a source doping region and a drain doping region within the semiconductor substrate outside the spacer. Finally, a second RTA process is performed to simultaneously activate dopants in the source extension doping region, the drain extension doping region, the source doping region and the drain doping region.
As the first ion implantation process uses an implantation energy that is greater than the implantation energy of the second implantation process, the first RTA process is performed immediately after the first ion implantation process to activate ions within the semiconductor substrate and repair damages on the crystal lattice structure. As a result, TED effects and thermal diffusions of the high-energy ions in the pocket implant region are prevented from affecting the junction depth of the source extension and the drain extension.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 4801555 (1989-01-01), Holly et al.
patent: 6258682 (2001-07-01), Tseng
patent: 6265255 (2001-07-01), Hsien
patent: 6323077 (2001-11-01), Guo
Lai Han-Chao
Lin Hung-Sui
Lu Tao-Cheng
Hsu Winston
Lindsay Jr. Walter L.
Macronix International Co. Ltd.
Niebling John F.
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