Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-08
2002-12-10
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S401000, C438S462000, C438S678000
Reexamination Certificate
active
06492269
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to a copper plating method, whereby the wafer edge alignment marks for subsequent processing steps are protected from being covered by copper deposition by two methods: the first method being that of forming alignment mark shields at the wafer's edge, thus preventing both barrier and copper seed layers from being deposited in those regions; the second method being that of forming small pad-like extrusions at the contact ring of the copper plating fixture, thus preventing copper plating at the contact points.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 5,933,758 entitled “Method For Preventing Electroplating Of Copper On An Exposed Surface At The Edge Exclusion Of A Semiconductor Wafer” granted Aug. 3, 1999 to Jain describes a process for not plating Cu on the outside edge of a wafer. A layer is in situ covered with a copper seed layer. The layer is not formed in an edge exclusion region, thereby exposing a portion of the layer. This portion will natively oxidize in a room ambient to form a copper electroplating prevention barrier, whereby copper will not electroplate in the region.
U.S. Pat. No. 6,049,137 entitled “Readable Alignment Mark Structure Formed Using Enhanced Chemical Mechanical Polishing” granted Apr. 11, 2000 to Jang et al. describes a chemical mechanical polish (CMP) process for an alignment mark area. A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate is disclosed. Alignment mark trenches are formed in the substrate. An insulating layer is formed over the alignment mark area. The insulating layer is chemical mechanical polished (CMP), thereby removing a first thickness of the insulating layer from the alignment mark area, leaving a residual insulating layer in the alignment mark trenches. Etches are used to remove the residual insulating layer, a silicon nitride layer, and a pad oxide layer in the alignment mark area, thereby exposing the alignment marks and making the alignment marks readable.
U.S. Pat. No. 4,632,724 entitled “Visibility Enhancement Of First Order Alignment Marks” granted Dec. 30, 1986 to Chesebro et al. teaches an alignment mark process that forms a “block mask” over the alignment mark areas. After a given mark is formed, it is tested for visual contrast. If the contrast is insufficient to provide adequate alignment, a block mask is formed on a “critical mask”. The block mask exposes all of the alignment target areas and protects the product regions of the wafer, and the “critical mask” only exposes the mark to be enhanced. The mark is then etched for a time period which is a function of the measured visual contrast, to enhance the alignment marks.
U.S. Pat. No. 6,057,206 entitled “Mark Protection Scheme With No Masking” granted May 2, 2000 to Nguyen et al. teaches an alignment mark protection scheme that forms an alignment mark protection layer over the alignment mark. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer, which does not overlie the alignment mark. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion using an “edge-bead removal tool”. Therefore, the scheme allows for the formation of an alignment mark protection structure without an extra masking step.
U.S. Pat. No. 5,897,371 entitled “Alignment Process Compatible With Chemical Mechanical Polishing” granted Apr. 27, 1999 to Yeh et al. describes an alignment mark process with chemical mechanical polish (CMP), that deposits metal over the alignment marks. The invention discloses a process that maintains a second (or “replica”) set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including chemical mechanical polish (CMP) and other planarization methods. The method describes a new alignment mark that may be “printed” in a metal layer on the wafer. The new alignment mark is generally not subjected to planarization or to an “open frame” process.
U.S. Pat. No. 5,899,738 entitled “Method For Making Metal Plugs In Stacked Vias For Multilevel Interconnections and Contact Openings While Retaining The Alignment Marks Without Requiring Extra Masking Steps” granted May 4, 1999 to Wu et al. teaches an alignment mark process that removes metal from over alignment marks. The method discloses the formation of stacked metal plugs in via holes and contacts, while retaining alignment marks without using additional masking steps. The method involves the deposition of a barrier layer and a tungsten layer, which fill the via boles or contact openings in an insulating layer. The tungsten is then etched back, without over-etching, to the surface of the barrier layer to form tungsten plugs that are coplanar with the surface of the insulating layer. Concurrently, the tungsten is removed from the recessed alignment marks, which allows for the replication of the alignment marks in the next level of metal, thereby eliminating additional masking steps.
SUMMARY OF THE INVENTION
This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to a copper plating method, whereby the wafer edge alignment marks for subsequent processing steps are protected from being covered by copper deposition by two methods: the first method being that of forming alignment mark shields at the wafer's edge, thus preventing both barrier and copper seed layers from being deposited in those regions; the second method being that of forming small pad-like extrusions at the contact ring of the copper plating fixture, thus preventing copper plating at the contact points. In the first method, an alignment mark shield is utilized to cover the alignment mark areas, near the edge of the wafer, with a mechanical shield. This shield protects the alignment mark regions from film deposition during the sputter deposition steps of barrier and copper seed layers. The alignment marks are left without a copper seed layer, hence preventing copper deposition in these regions during copper electroplating. In the second method, the alignment mark areas, near the edge of the wafer, are protected from copper electroplating deposition by use of small pad-like extrusions positioned at copper plating contact ring. The pad-like extrusion is part of the contact ring and prevents copper buildup and deposition on the alignment mark.
In the first method, that is the use of an alignment mark shield, the key elements follow. As a background, one of the problems the present invention addresses is the problem of a recessed profile at the alignment mark area before copper damascene processing which leads to a copper and barrier layer remaining after the chemical mechanical polishing (CMP) of copper. In addition, during the electrochemical plating of copper higher currents occur at the cathode contact at the wafer's edge, which leads to a steep convex copper profile at the wafer's edge and residual copper remains after the chemical mechanical polishing (CMP) of copper. However, by using an alignment mark shield at copper seed and barrier sputter deposition steps, the electrochemical plating of copper (ECP-Cu) will not occur on the underlying dielectric layer. Hence a clean and transparent area at alignment mark can be achieved at post chemical mechanical polishing (CMP) of copper.
In the second method, the alignment mark areas, near the edge of the wafer, are protected from copper electroplating deposition by use of small pad-like extrusions positioned at copper plating contact ring. The key elements follow. The pad-like extrusion is part of the contact ring and prev
Hsieh Ching-Hua
Liu Chung-Shi
Shue Shau-Lin
Yu Chen-Hua
Ackerman Stephen B.
Nguyen Ha Tran
Taiwan Semiconductor Manufacturing Company
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