Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-23
2002-10-29
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S307000, C438S595000, C438S981000
Reexamination Certificate
active
06472284
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to a semiconductor device and a method for fabricating a semiconductor device, particularly a method for fabricating a MOS transistor.
2. Description of the Background Art
Thinning of a gate insulating film and increasing impurity concentration causes an increase in internal electric fields unless the source voltage is scaled, High electric fields consequently cause a variety of physical problems. A high electric field around a drain causes an electron-hole pair (due to collisional ionization), hot carrier implantation into a gate insulating film, tunneling between bands, etc. Accordingly, the reliability of a MOS transistor is compromised.
Thus, one of the main problems in designing the structure of an MOS transistor involves developing a drain structure for alleviating a high electric field around a drain. To solve this problem, a semiconductor device having a LDD (lightly doped drain) structure is developed.
A method for fabricating a semiconductor device having a LDD structure according to the conventional art is described below with reference to the accompanying drawings.
FIG. 1A
illustrates a gate oxide film
101
and a gate electrode
102
being consecutively formed on the upper surface of a semiconductor substrate
100
.
Next, as illustrated in
FIG. 1B
, a buffer oxide film
103
is formed on the front surface of the structure of
FIG. 1A
, and thereafter phosphor (P) ions are implanted into the semiconductor substrate
100
, thereby forming a lightly doped impurity region, e.g., a lightly doped drain (LDD) region
104
in the semiconductor substrate
100
at both sides of the gate electrode
102
. Here, the lightly doped region
104
refers to a region whose impurity concentration is relatively lower than that of a source/drain to be fabricated in a subsequent process. That is, lightly doped region
104
is a lightly doped ion implantation region. The source/drain region is hereafter referred to as a heavily doped ion implantation region.
Next, as illustrated in
FIG. 1C
, an oxide film or nitride film is formed on the upper surface of the structure in
FIG. 1B
by high temperature low pressure chemical vapor deposition. Afterwards, anisotropic etching is carried out on the nitride film without using an etching mask, thereby forming a side wall spacer
105
at both side walls of the gate electrode
102
. The anisotropic etching can be carried out at a uniform thickness.
Next, as illustrated in
FIG. 1D
, a heavily doped region
106
, e.g., a source/drain, is formed in the semiconductor substrate
100
at the outer side of the side wall spacer
105
by implanting arsenic (As) ions into the semiconductor substrate
100
, thus completing the fabrication of a n-type MOS transistor. The heavily doped region
106
denotes a region having a relatively higher impurity concentration than that of the lightly doped region
104
.
However, the semiconductor device fabricated by the conventional method has the following problems.
When ion implantation is used for forming a LDD region, the ion implantation is carried out when the buffer oxide film covers the gate electrode causing the overlap length of the gate electrode and LDD region to decrease as much as the thickness of the buffer oxide film. This causes an increase of horizontal electric fields of a channel, and a hot carrier is implanted into the gate insulating film, thereby causing degradation of the device characteristics and serious reliability problems. In addition, there is a problem that the refresh time characteristic deteriorates due to the high electric field.
SUMMARY OF THE INVENTION
Accordingly, the invention, in part, provides a method for fabricating a MOS transistor which improves the refresh time characteristic and alleviates the hot carrier effect problem by increasing the overlap length of a LDD region and gate electrode and reducing a horizontal electric field of a channel. Accordingly, the side walls at both sides of the gate electrode do not completely cover a buffer oxide film.
The invention, in part, provides a semiconductor device (MOS transistor) having an improved refresh time characteristic by reducing the junction concentration of a LDD region and increasing the overlap length of the LDD region and a gate electrode. The horizontal electric field of a channel is thereby reduced, and hot carrier resistance intensifies by forming a thick pad oxide film at both sides of the gate electrode, thereby preventing hot carrier ion implantation into a gate insulating film.
In addition, the invention, in part, provides a method for fabricating a MOS transistor that reduces the impurity ion concentration of a LDD region by deeply forming a LDD junction in a semiconductor substrate using a cascade pad oxide film. Accordingly, the refresh time characteristic improves by increasing depletion width for thus alleviating an electric field around a channel.
To achieve the above, the MOS transistor fabrication method according to the invention includes the steps of: forming a pad oxide film on the upper surface of a semiconductor substrate; forming a HLD film on the upper surface of the pad oxide film; forming an opening which a gate electrode to be desired to be formed fits in by selectively etching the HLD oxide film; forming a nitride side wall spacer on side walls of the HLD film within the opening; etching and removing the pad oxide film within the opening; forming a gate oxide film at a portion from which the pad oxide film is removed; forming a gate electrode by filling the opening on the upper surface of the gate oxide film with a gate electrode material layer; etching the HLD film; etching the pad oxide film formed at a lower portion of the HLD film at a predetermined thickness; removing the nitride side wall spacer; forming a LDD region by implanting impurity ions into the semiconductor substrate at both sides of the gate electrode; forming a side wall spacer at both sides of the gate electrode; and forming a source/drain by implanting impurity ions into the semiconductor substrate using the side wall spacer as a mask.
To achieve the above, the MOS transistor fabrication method according to the invention further includes a step of forming a punch through stop layer in the semiconductor substrate within the opening by implanting impurity ions into the semiconductor substrate via the opening. This step is performed after the step of forming a nitride side wall spacer on the HLD side walls.
To achieve the above, the MOS transistor fabrication method according to the invention further includes the step of forming a threshold voltage control layer on an upper portion of the punch through stop layer in the semiconductor substrate in the opening.
To achieve the, the MOS transistor fabrication method according to the invention further provides the gate electrode being formed as a polysilicon, silicide, or polycide layer.
To achieve the above, the MOS transistor fabrication method according to the invention further provides that the step of etching the pad oxide film formed at a lower portion of the HLD film at a predetermined thickness is a step of etching the pad oxide film at about half the overall thickness thereof.
To achieve the above, the MOS transistor fabrication method according to the invention further includes the step of forming a halo ion implantation layer so as to cover the LDD region after the step of forming the LDD region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4855247 (1989-08-01), Ma et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5538913 (1996-07-01), Hong
patent: 5750430 (1998-05-01), Son
patent: 5773348 (1998-06-01), Wu
Birch & Stewart Kolasch & Birch, LLP
Chaudhari Chandra
Hynix / Semiconductor Inc.
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