Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-04
2002-10-01
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S304000, C438S752000, C438S149000, C438S268000
Reexamination Certificate
active
06458662
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION(S)
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
REFERENCE TO A MICROFICHE APPENDIX
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the formation of complimentary metal oxide semiconductor field effect transistors (MOSFETs). Even more particularly, the present invention relates to forming MOSFETs using differential silicides.
2. Description of the Background Art
Currently, a double-gate silicon-on-insulator metal oxide semiconductor field effect transistor (SOI MOSFET) is receiving significant attention in the semiconductor industry due to its high current drive and high immunity to short-channel effects. As such, the dual-gate SOI MOSFET is a good candidate architecture for sub-0.25-&mgr;m gate length complementary metal oxide semiconductor (CMOS) technology. A dual-gate Fin-FET comprises an active layer being surrounded by a gate on both sides of a narrow silicon “fin.” However, only one gate electrode straddles across the silicon “fin” or active line. In some applications, a separate gate electrode may be required. By individually biasing two such gates (i.e., applying an “asymmetrical gate”), the threshold voltage of a MOSFET is more readily controllable. Dual-gate biasing of a transistor also potentially reduces standby power and/or improves on-state drive current through a “threshold dynamic voltage” design. However, these related art dual gates have limited carrier mobility (speed at which an electron or a hole can move). Therefore, a need exists for a method of fabricating a semiconductor device having an asymmetrical dual-gate MOSFET with a channel which improves carrier mobility.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a semiconductor device having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel which improves carrier mobility, and a device thereby formed. Generally, the present invention device comprises a SiGe channel, which provides approximately 2 to 5 times more carrier mobility (especially with “holes”) than a related Si channel, because the present SiGe channel reduces carrier scattering and has a substantially lighter effective mass of “holes.” The present invention method for fabricating the present device, generally comprises: forming a dual-gate MOSFET having a SiGe/Si/SiGe sandwich structure; and forming a pair of asymmetrical gate electrodes. The unique features of the present method basically involve forming an epitaxial layer, comprising SiGe, on at least one sidewall of a narrow line, comprising Si; depositing a gate electrode material over the narrow line and the epitaxial layer; and polishing the gate electrode material, and thereby forming the pair of asymmetrical gate electrodes. This present invention dual-gate device, so formed, has the advantages of both a high drive current as well as a high immunity to short-channel effect (SCE), enabling further densification of transistors and circuits.
By way of example, and not of limitation, a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel, may be fabricated according to the present invention by: (a) patterning an active region of a silicon-on-insulator (SOI) structure (or wafer) with a first photoreist layer, wherein the SOI structure comprises a silicon dioxide (SiO
2
) layer, a silicon (Si) layer deposited on the SiO
2
layer, and a silicon nitride (Si
3
N
4
) layer deposited on the Si layer; (b) initiating formation of a SiGe/Si/SiGe sandwich fin structure from the SOI structure, wherein the step (b) comprises (b)(1) etching through the Si
3
N
4
and the Si layers, thereby forming a Si
3
N
4
/Si stack, the Si
3
N
4
/Si stack comprising a Si
3
N
4
cap layer and a reduced width Si layer, wherein the Si
3
N
4
/Si stack has a height in a range of approximately 800 Angstroms to approximately 1500 Angstroms, and (b)(2) further etching the Si layer by wet-etching, thereby forming a narrow line, comprising Si, under the Si
3
N
4
cap layer; (c) completing formation of the SiGe/Si/SiGe sandwich fin structure, wherein the step (c) comprises (c)(1) forming an epitaxial layer, comprising SiGe, on at least one sidewall of the narrow line, and (c)(2) depositing a thin gate dielectric layer, wherein the thin gate dielectric layer comprises a high dielectric constant material such as Si
3
N
4
; (d) depositing a thick gate material layer on SiGe/Si/SiGe sandwich fin structure, wherein the thick gate material layer has a thickness in a range of approximately 3000 Angstroms to approximately 6000 Angstroms, and wherein the thick gate material layer comprises a material selected from a group consisting essentially of polysilicon (poly-Si), poly-SiGe, and a metal; and (e) forming an asymmetrical dual gate, wherein the step (e) comprises (e)(1) polishing the gate material, thereby forming a polished gate material, whereby the Si
3
N
4
cap layer acts as a polishing-stop, wherein the polishing step (e)(1) may be performed by a technique such as chemical-mechanical polishing (CMP), (e)(2) patterning the polished gate material with a second photoreist layer; (e)(3) etching the patterned polished gate material, thereby forming a pair of asymmetrical gate electrodes, and (e)(4) completing processing of the asymmetrical gate electrodes, thereby forming the asymmetrical dual-gate, wherein the asymmetrical dual gate is separated by the Si
3
N
4
cap layer; and (f) completing fabrication of the semiconductor device (e.g., formation of source/drain structure).
An object of the present invention is to reduce carrier scattering and provide a substantially lighter effective mass of “holes” in a MOSFET.
Another object of the present invention is to provide a method for fabricating a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel which improves carrier mobility.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.
REFERENCES:
patent: 6200866 (2002-03-01), Ma et al.
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Tsai Jey
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