Heater temperature uniformity qualification tool

Coating apparatus – Gas or vapor deposition – Work support

Reexamination Certificate

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Details

C118S666000, C118S696000, C118S697000, C118S715000, C118S725000

Reexamination Certificate

active

06500266

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of integrated circuits and, more particularly, to process parameter uniformity within an environment for fabricating integrated circuits.
2. Background
High density integrated circuits, such as very large scale integration (VLSI) devices are typically formed on semiconductor substrates or wafers by subjecting the wafers to a number of deposition, masking, doping, and etching processes. In a typical single-wafer processing chamber or reactor, a wafer is placed onto a stage or susceptor within a process chamber and process gases are delivered into the chamber onto the wafer to perform the various deposition and etching steps. Chemical vapor deposition (CVD), for example, is a common process for depositing various types of films on substrates or wafers. In typical CVD processing, a wafer is placed in a deposition or reaction chamber and reactant gases are introduced into the chamber and are decomposed and reacted at a heated surface to form a thin film on the wafer. For example, one CVD process involves delivering silane (SiH
4
) and ammonia (NH
3
) into a process chamber while applying resistive or radiant heat to form silicon nitride on a wafer.
One consideration in semiconductor processing, including the fabrication of integrated circuits on a wafer, is the application of process gases in a uniform and controlled manner across the wafer's entire surface. This consideration is important in the fabrication of VLSI devices since a large number of processing steps are generally performed in sequence. A wafer may be comprised of dozens of areas designated as similar or identical chips or devices. Process parameter uniformity is therefore important to reliably make a chip on one portion of an area of a wafer similar to another chip on another area portion of the wafer.
The deposition rate, thickness, and uniformity of films formed on a wafer may depend on a variety of parameters such as the pressure or the temperature in the chamber, or the amount and type of gas and flow rate of gas across the wafer introduced into a chamber. Additionally, increasing a parameter such as temperature may affect another parameter such as pressure. For example, using a higher temperature generally allows for a higher pressure to be used.
In low pressure CVD (LPCVD) reactions, temperature uniformity is generally important. The surface reaction associated with a CVD process can generally be modeled by a thermally activated phenomenon that proceeds at a rate, R, given by the equation:
R=R
0
e
[−E
a
/kT]
where R
o
is the frequency factor, E
a
is the activation energy in electron volts (eV), and T is the temperature in degrees Kelvin. According to this equation, the surface reaction rate increases with increasing temperature. In a LPCVD process such as a Si
3
N
4
deposition, the activation energy (E
a
) is generally very high, on the order of 0.9-1.3 eV. Accordingly, to obtain a uniform thickness across the wafer, the temperature uniformity across the wafer should be tightly controlled, preferably on the order of ±2.5° C. or less for temperatures around 750° C.
One common heating scheme in CVD systems is a resistive heating scheme. A resistive heating scheme in a single-wafer chamber generally incorporates the resistive heating element directly in the stage or susceptor that supports the wafer in the chamber. In this manner, the reaction produced during the deposition may be generally more localized at the wafer. The heating element is typically a thin layer of conductive material, such as a thin coiled layer (about 2 mils) of a molybdenum (Mo) material formed in a single plane of the body of the susceptor. This design may be described as a “single-zone resistive heater,” the “zone” description referring to the location of the heating element in a single plane in the body of the stage or susceptor. The CVD reaction in which the resistive heaters are used typically has a temperature compatibility to approximately 550° C. At higher temperatures, e.g., 750° C., temperature uniformity becomes problematic. One reason is that heat loss in a resistive heater increases with higher temperatures, particularly at the edges of the stage or susceptor. Single-zone resistive heaters typically do not have the ability to compensate for differences in heat loss across the stage or susceptor.
A second problem with single-zone resistive heaters such as described above and temperatures of 750° C. is localized heating. At high temperatures, single-zone heaters exhibit concentrated localized heating associated with high density power applied to the heating element at a localized area. Consequently, temperature uniformity is affected. A third problem with single-zone resistive heaters is that variations in manufacturing of the heating element can cause fluctuations in performance of a heating element which can lead to non-uniformity. The single-zone heater cannot be adjusted to compensate for the manufacturing variation. Further, at high temperature operation, single-zone heaters have shorter lifetimes due to the high power density applied at the power terminals and to the heating elements.
What is needed is a heating scheme for a processing chamber compatible with high temperature operation, e.g., on the order of 700° C. or greater, that achieves high temperature uniformity localized at a reaction site. What is also needed is a mechanism for evaluating the temperature uniformity of a reaction chamber or a heater within a reaction chamber.
SUMMARY OF THE INVENTION
An apparatus, a method, and a system are disclosed. In one embodiment, the apparatus is a reactor or processing chamber comprising a chamber having a resistive heater disposed within a volume of the chamber. The resistive heater includes a stage having a surface area to support a substrate such as a wafer and a body including at least one heating element. The resistive heater also includes a shaft coupled to the body. The reactor includes a plurality of temperature sensors coupled to the chamber, each configured to measure a temperature at separate points associated with the surface area of the stage. Finally, the reactor includes a motor coupled to the shaft and configured to rotate the resistive heater about an axis through the shaft. In this manner, the temperature sensors may measure a temperature at separate points of the surface area of the stage. In one embodiment, the temperature sensors are aligned such that as the stage rotates 360°, the temperature sensors can read individual points defining concentric circles of the area of the stage or a wafer seated on the stage. Based on this data, a temperature map can be generated to show the temperature uniformity of the heater.
In an embodiment of the method of the invention, a reactor such as described is provided. The shaft is rotated and a plurality of temperatures are measured over the surface area of the stage or over a wafer seated on the stage with a plurality of temperature sensors. In this manner, the temperature uniformity of the resistive heater may be evaluated by, for example, generating a temperature map and comparing the temperature map with a desired map profile. Thus, the invention provides, in one embodiment, a tool to evaluate the temperature uniformity capability of the heater. By improving the temperature uniformity, the film formation on a wafer formed utilizing the heater may be improved.
Additional features, embodiments, and benefits will be evident in view of the figures and detailed description presented herein.


REFERENCES:
patent: 5273588 (1993-12-01), Foster et al.
patent: 5294778 (1994-03-01), Carman et al.
patent: 5329732 (1994-07-01), Karlsrud et al.
patent: 5421892 (1995-06-01), Miyagi
patent: 5487127 (1996-01-01), Gronet et al.
patent: 5708755 (1998-01-01), Gronet et al.
patent: 5715361 (1998-02-01), Moslehi
patent: 5840125 (1998-11-01), Gronet et al.
patent: 5937142 (1999-08-01), Moslehi et al.
patent: 6090210 (2000-07-01), Balance et al.
patent: 62221

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