Semiconductor device and fabricating the same

Details Semiconductor device and fabricating the same Semiconductor device and fabricating the same

2000-08-21

2002-12-10

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S287000

Reexamination Certificate

active

06492215

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a semiconductor device and a method of fabricating the same, and more particularly, to the structure of a semiconductor device provided with an N channel MOS device and a P channel MOS device, or a MONOS device in addition thereto which are all formed on top of a common semiconductor substrate, or a common SOI substrate, and a method of fabricating the same.
2. Description of the related Art
A MOS (Metal-Oxide-Semiconductor) device using a semiconductor substrate made of silicon, and the same using a semiconductor substrate having a semiconductor layer on top of an insulating layer formed on a supporting substrate, a so-called SOI (Silicon on Insulator) substrate are well known.
First, the structure of a conventional MOS device using a semiconductor substrate made of silicon is described by way of example with reference to a schematic cross sectional view shown in FIG.
69
.
The MOS device shown in
FIG. 69
comprises an N channel MOS device
11
, and a P channel MOS device
12
, which are both formed on a semiconductor substrate
1
made of silicon, making up a complementary MOS device.
The N channel MOS device
11
is provided with a gate oxide film
2
and gate electrode
3
formed on the surface of the semiconductor substrate
1
over a P well
4
formed of a p-type doped layer diffused in the semiconductor substrate
1
, and also with a source
6
and drain
7
, formed of a heavily doped n-type layer on the surface of the semiconductor substrate
1
, matching the gate electrode
3
.
The P channel MOS device
12
is provided with a gate oxide film
2
and gate electrode
3
formed on the surface of the semiconductor substrate
1
over an N well
5
formed of an n-type doped layer diffused in the semiconductor substrate
1
, and also with a source
16
and drain
17
, formed of a heavily doped p-type layer on the surface of the semiconductor substrate
1
, matching the gate electrode
3
.
The N channel MOS device
11
and P channel MOS device
12
are isolated from each other by a field oxide film
13
formed on the surface of the semiconductor substrate
1
.
An interlevel insulator
8
is formed on the entire surface of the semiconductor substrate
1
, and via contact holes
9
formed in the interlevel insulator
8
, connection to other MOS devices formed on the semiconductor substrate
1
is made with interconnections
10
(interconnection
10
connected to the gate electrodes
3
,
3
, respectively, is disposed at a position different in cross-sectional view from that shown in FIG.
69
), one end of which are connected to the gate electrode
3
, source
6
and drain
7
of the N channel MOS device
11
as well as the gate electrode
3
, source
16
and drain
17
of the P channel MOS device
12
, respectively.
Now the structure of a conventional MOS device using a SOI substrate is described by way of example with reference to a schematic cross sectional view shown in FIG.
70
.
The MOS device shown in
FIG. 70
makes use of the SOI substrate
23
comprising a supporting substrate
20
, an insulating film
21
, and a plurality of semiconductor layers
22
a
,
22
b
, each patterned in an island-like shape
A gate oxide film
2
and gate electrode
3
are formed on top of the respective semiconductor layers
22
a
, and
22
b
, making up a semiconductor device comprising an N channel MOS device
11
and a P channel MOS device
12
.
The N channel MOS device
11
is provided with a source
6
and drain
7
, formed of a heavily doped N type layer, in a region of the semiconductor layer
22
a
, matching a gate electrode
3
.
Similarly, the P channel MOS device
12
is provided with a source
16
and drain
17
, formed of a heavily doped P type layer, in a region of the semiconductor layer
22
b
, matching a gate electrode
3
.
The N channel MOS device
11
and the P channel MOS device
12
are completely isolated for insulation from each other with an interlevel insulator
8
and the insulating film
21
.
Then, via respective contact holes
9
formed in the interlevel insulator
8
, connection to other MOS devices formed on the SOI substrate
23
is made with interconnections
10
(interconnection
10
connected to the gate electrodes
3
,
3
, respectively, is disposed at a position different in cross-sectional view from that shown in FIG.
70
), one end of which is connected to the gate electrode
3
, source
6
and drain
7
of the N channel MOS device
11
as well as the gate electrode
3
, source
16
and drain
17
of the P channel MOS device
12
, respectively.
Next, the structure of a conventional semiconductor device incorporating a MONOS device in addition to the semiconductor device shown in
FIG. 69
is described by way of example with reference to FIG.
71
.
In the semiconductor device shown in
FIG. 71
, an N channel MOS device
11
, a P channel MOS device
12
, and a MONOS device
35
are formed on a semiconductor substrate
1
made of silicon.
The N channel MOS device
11
is provided with a gate oxide film
2
and gate electrode
3
formed on the surface of the semiconductor substrate
1
over a P well
4
formed of a p-type doped layer diffused in the semiconductor substrate
1
, and also with a source
6
and a drain
7
, formed of a heavily doped n-type layer on the surface of the semiconductor substrate
1
, matching the gate electrode
3
.
The P channel MOS device
12
is provided with a gate oxide film
2
and gate electrode
3
formed on the surface of the semiconductor substrate
1
over an N well
5
formed of an n-type doped layer diffused in the semiconductor substrate
1
, and also with a source
16
and a drain
17
, formed of a heavily doped p-type layer on the surface of the semiconductor substrate
1
, matching the gate electrode
3
.
The MONOS device
35
is provided with a memory insulating film
34
comprising a memory oxide film
31
, a memory nitride film
32
, and a top oxide film
33
, and also with a memory gate electrode
50
, which are all formed on the surface of the semiconductor substrate
1
over a P well
4
formed of a p-type doped layer diffused in the semiconductor substrate
1
, and also with a source
7
(for common use as the drain
7
of the N channel MOS device
11
) and a drain
18
, formed of a heavily doped n-type layer on the surface of the semiconductor substrate
1
, matching the memory gate electrode
50
.
The P channel MOS device
12
, N channel MOS device
11
, and MONOS device
35
are isolated from each other with field oxide films
13
formed on the surface of the semiconductor substrate.
An interlevel insulator
8
is formed on the entire surface of the semiconductor substrate
1
and via contact holes
9
formed in the interlevel insulator
8
, connection to other MOS devices formed on the semiconductor substrate
1
is made with interconnections
10
, ends of which are connected to the gate electrodes
3
, the sources
6
,
16
and the drains
7
,
17
,
18
of the respective semiconductor devices
11
,
12
, and
35
.
A method of fabricating the semiconductor device shown in
FIG. 71
is described hereinafter with reference to
FIGS. 72 through 76
, which are cross-sectional views showing respective steps of a fabrication process.
The first half of the fabrication process of the semiconductor device described above comprises the same steps as those of a third embodiment of a method of fabricating a semiconductor device according to the invention as described hereinafter with reference to
FIGS. 29 through 34
. Accordingly, illustration of these steps is omitted, and the fabrication process is described with reference to
FIG. 72
only.
First, by oxidizing the semiconductor substrate
1
made of silicon in an oxidizing atmosphere, an oxide film is formed on the surface thereof
Subsequently, a photo-resist which is a photosensitive polymer is formed on the entire surface of the oxide film by use of a spin coater, and by applying exposure and development treatment thereto with the use of a predetermined mask, the photo-resi

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