Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-04
2002-02-19
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S132000
Reexamination Certificate
active
06348398
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming pad openings and fuse openings on the surface of a wafer. More particularly, the present invention relates to a method of forming pad openings and fuse openings on the surface of a wafer in a single photolithographic process.
2. Description of Related Art
A conventional method of forming pad openings and fuse openings on the surface of a wafer having bonding pads and safety fuses thereon includes sequentially forming a passivation layer and a photoresist layer over the wafer. This is followed by conducting photolithographic and etching processes to form the required openings over the pads and the fuses.
In the photolithographic and etching processes, the pad openings must be over-etched so that the passivation layer on the surface of each pad is completely removed and the underlying metallic layer is exposed. Similarly, the bottom of fuse openings and the space between the fuses are protected by a thick layer of passivation layer. However, the passivation layer on top of the pads and the passivation layer on top of the fuses are made from identical material in a single deposition process. Hence, the two passivation layers have identical thickness. Since both passivation layers are subjected to identical etching during photolithographic and etching processes, the fuses are exposed besides the pads. Thus, the wafer circuit is out of specification with the original design resulting in a drop in production yield.
In addition, resistance to etching for the passivation layer over pads is much higher than the passivation layer elsewhere. This is due to an additional photoresist layer over the passivation layer around the pad area. Because the area around the fuses is not protected by photoresist material, over-etching of the passivation layer on each side of the fuses to form trenches is highly likely. Ultimately, wafer circuit is damaged and production yield is lowered.
To reduce the over-etching problems, the etching process is slightly changed. A passivation layer and a photoresist layer are sequentially formed over a wafer having pads and fuses thereon. Thereafter, separate photolithographic and etching processes each having a different degree of etching are conducted to form the pad openings and the fuse openings.
Although the improved etching method can overcome the over-etching problem, two separate photolithographic and etching processes have to be conducted. This not only increases production time, but also increases cost of production.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming pad openings and fuse openings over a wafer using a single photolithographic and etching operation. Hence, some processing steps are saved, production yield is increased and production cost is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming pad openings and fuse openings over a wafer. A wafer having pads and fuses thereon is provided. A passivation layer and a photoresist layer are sequentially formed over the wafer. A photo-exposure and development operation is carried out to remove the photoresist layer above the pads. An etching operation is conducted to remove the passivation layer above the pads as well as the photoresist layer and a portion of the passivation layer above the fuses. Finally, the photoresist layer is removed.
In this invention, a definite thickness of the photoresist layer is retained over the fuses after photo-exposure and development. In subsequent etching processes, etchants are prevented from over-etching and exposing the fuses while a pad over-etching operation is conducted. Since a passivation layer having a definite thickness is always retained at the bottom of the fuse opening and on each side of the fuses after the etching step, the fuses are protected from exposure. Ultimately, production yield of the wafer is increased and cost of production is lowered.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5985765 (1999-11-01), Hsiao et al.
patent: 6235557 (2001-05-01), Manley
J.C. Patents
Tsai Jey
United Microelectronics Corp.
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