Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-08
2002-11-19
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S381000, C438S686000
Reexamination Certificate
active
06482736
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and the fabrication thereof, and particularly to ruthenium-containing conductive layers and the formation and use thereof.
BACKGROUND OF THE INVENTION
A capacitor generally includes two electrical conductors in close proximity to, but separated from, each other. The two conductors form the “plates” of the capacitor, and may be separated by a dielectric material. When a voltage is applied across the plates of a capacitor, electrical charge accumulates on the plates. If the plates are electrically isolated essentially immediately after a voltage is applied, the accumulated charge may be stored on the plates, thus “storing” the applied voltage difference.
The fabrication of integrated circuits involves the formation of conductive layers for use as various circuit components, including for use as capacitor plates. Memory circuits, such as DRAMs the like, use conductive layers to form the opposing plates of storage cell capacitors.
The drive for higher-performance, lower-cost integrated circuits dictates ever-decreasing area for individual circuit features, including storage capacitors. Since capacitance of a capacitor (the amount of charge that can be stored as a function of applied voltage) generally varies with the area of capacitor plates, as the circuit area occupied by the storage capacitor decreases, it is desirable to take steps to preserve or increase capacitance despite the smaller occupied area, so that circuit function is not compromised.
Various steps may be taken to increase or preserve capacitance without increasing the occupied area. For example, material(s) having higher dielectric constant may be used between the capacitor plates. Further, the plate surfaces may be roughened to increase the effective surface area of the plates without increasing the area occupied by he capacitor.
One method for providing a roughened surface for a plate of a storage cell capacitor is to form the plate of hemispherical grain polysilicon (HSG), possibly with an overlying metal layer. The hemispherical grains of HSG enhance the surface area of the plate without increasing its occupied area.
HSG presents difficulties in fabrication, however, because of the formation of silicon dioxide on and near the HSG. A silicon dioxide layer may form on the HSG, particularly during deposition of the capacitor's dielectric layer. Even with an intervening metal layer present, oxygen from the deposition of the dielectric layer can diffuse through the metal layer, forming silicon dioxide at the polysilicon surface. Silicon diffusion through the metal layer may also produce a silicon dioxide layer between the metal and the dielectric layers.
Silicon dioxide between the metal layer and the HSG can degrade the electrical contact to the metal capacitor plate surface. Silicon dioxide between the metal layer and the dielectric layer can decrease the capacitance of the resulting capacitor.
To attempt to avoid these negative effects caused by formation of silicon dioxide, a diffusion barrier layer may be employed between the HSG and the metal layer. But in the typical capacitor geometry, the greater the total number of layers, the larger the required minimum area occupied by the capacitor. Further, the upper surface of each additional layer deposited over the HSG tends to be smoother than the underlying surface, reducing the increased surface area provided by the HSG.
SUMMARY
The present invention provides an enhanced-surface-area (rough-surfaced) conductive layer compatible with high-dielectric constant materials and useful in the formation of integrated circuits, particularly for plates of storage capacitors in memory cells.
The enhanced-surface-area conductive layer may be formed by first forming a film having two or more phases, such as iridium and iridium oxide phases, ruthenium and ruthenium oxide phases, rhodium and rhodium oxide phases, platinum and platinum-rhodium phases, and the like. The film may be formed over an underlying conductive layer. At least one of the phases in the film is then selectively removed from the film, leaving at least one of the phases behind to form an enhanced-surface-area conductive layer.
In an illustrated embodiment, a phase of a layer is removed to leave a pitted surface of a non-removed phase. The pitted surface may include islands formed of the non-removed phase. An “islanded” surface may also be formed by the differential removal, the surface of which may include some pits. Any suitable selective removal process may be employed, such as an etch process or etchant, wet or dry, that etches one phase at a much greater rate than an other phase. Thermal and electrochemical selective removal techniques may also be employed. The selective removal process preferentially removes the one phase, leaving a pitted or “islanded” surface of the other phase. In the case of an islanded surface having separate or isolated islands, an underlying conductive layer may physically and electrically connect the islands. The layer of remaining pitted or islanded material, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area electrically conductive layer.
The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. If the material chosen to form the enhanced-surface-area conductive layer is relatively resistant to oxidation-induced decreases in conductivity, such as with ruthenium oxide or other oxygen-containing conductors, for example, then the tendency toward silicon dioxide formation may be reduced or eliminated, providing improved compatibility for use with high-dielectric-constant dielectric materials. An intervening metal layer and/or barrier such as used in the HSG approach may also be used, but is desirably omitted from the capacitor structure, allowing smaller dimensions for capacitors with the same or even greater capacitance. This allows the design and fabrication of higher speed, higher density, and lower cost memory circuits.
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Basceri Cem
Cummings Steven D.
Graettinger Thomas M.
Visokay Mark
Ghyka Alexander
Klarquist & Sparkman, LLP
Micro)n Technology, Inc.
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