Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-31
2002-12-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S301000, C438S303000, C438S585000
Reexamination Certificate
active
06495406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to process for fabricating MOS integrated circuits, and, more particularly, to MOS or CMOS integrated circuits having a lightly doped drain (LDD) structure in which a portion of the drain nearest the channel is less strongly doped than other regions of the source and drain.
2. State of the Art
In the manufacture of high density integrated circuits using metal oxide semiconductor field effect transistor (MOSFET) technology, as device dimensions decrease, there is a need to create shallower source and drain junctions. However, correspondingly abrupt or steep n
+
doping profiles in NMOS transistor lead to increased electric fields in the device channel in a region adjacent to the drain. The high electric field causes electrons in the device channel to gain significant energy and be injected into the gate oxide. This phenomenon is also known as the “hot carrier” effect that leads to long term device degradation, threshold shifts, and poor reliability.
In lightly doped drain (LDD) structures, regions of the source and drain near the channel are less heavily doped than regions of the source and drain farther away from the channel. The lateral grading of the n
+
doping profile provided by lower doping near the gate electrode reduces the electric fields near the drain, improves the speed and reliability of the device, lowers the gate-source and gate-drain capacitance, and minimizes hot electron injection into the gate.
In a conventional LDD process, the gate electrode is used as a mask for the n
−
LDD implantation. Subsequently, sidewall oxide spacers are formed creating a narrower open region laterally spaced from the gate electrode in which a heavier source/drain implant is performed. In this manner, the LDD region is formed and the sidewall spacer can be retained preventing the damage caused by the sidewall spacer removal.
In processes in which the heavily doped drain is formed after the LDD implant, the LDD region will be subject to all thermal processing required to anneal and drive in the heavier drain implant. This loss of control results in diffusive broadening of the LDD region during high temperature treatments. However, the high dose source/drain implants, which in the conventional LDD process are performed after the LDD implant and spacer formation, must be annealed at high temperature to remove ion implantation damage.
Alternative processes are known that form the LDD region after the source/drain implant. In one process, the LDD region surrounding the gate electrode is masked with a layer slightly thicker than the gate to protect regions of the silicon adjacent to the gate electrode. Regions of the silicon further out are then doped with a first doping process and the mask removed to allow a lighter doping of the regions nearer the gate with a second doping process. In another known LDD process, a region of silicon dioxide is formed as a sacrificial or disposable spacer along the sides of the gate electrode and the silicon left exposed by the spacer is heavily doped to form source/drain regions. The disposable spacer is removed to expose regions near the gate previously covered by the spacers. The regions near the gate are then lightly doped with a second doping process.
Unfortunately, the etch used to remove the spacers causes damage in the gate oxide. Damage to the gate oxide significantly impacts yield and reliability. Another problem in the conventional processes using sidewall spacers is that substrate damage occurs in the LDD region during the sidewall spacer etch. Sidewall formation is accomplished by anisotropic etching using plasma techniques. Exposed silicon during the plasma etch is damaged requiring subsequent anneal, or damage removal processing to eliminate leakage and other electrical deficiencies caused by the defects. What is needed is a lightly doped drain process that allows formation of the heavily doped source/drain and sidewall due to sidewall spacers and the associated anneal processes while allowing independent control of the thermal budget for the LDD region.
SUMMARY OF THE INVENTION
Briefly stated, the present invention involves a lightly doped drain (LDD) process for forming MOS or CMOS transistors. A substrate with appropriate field oxide regions formed thereon is provided. A gate insulator layer is formed on active areas of the substrate. A first gate electrode layer preferably comprising polysilicon is formed over the gate oxide layer. An etch stop layer is formed on the upper surface of the first gate electrode layer. A second gate electrode layer covers the etched stop layer. Optionally, an oxide layer is formed covering the second gate electrodes layer. The oxide layer, if used, in the second gate electrode layer are patterned using conventional photoresist technology and etched so as to stop on the etch stop layer.
In this manner, the gate pattern is transferred to the semiconductor device, but the gate electrode is not completely formed. The spacer oxide layer is deposited over the partially etched gate electrode structure. The deposited oxide is anisotropically etched to form sidewall spacers covering the lateral sidewalls of the partially etched gate electrode. A high current source/drain implant is performed through the etch stop layer, the first gate electrode layer, and the gate oxide layer to form heavily doped portions of source and drain regions. Subsequently, the sidewall spacer is removed in a process that stops on the etch stop layer.
A relatively low concentration of impurities are implanted into the substrate through the etch stop, first gate electrode, and gate oxide layer. The etch stop, first gate electrode, and gate oxide layers are etched using the partially formed gate electrode as a mask to completely form the gate electrode. The LDD structure formed in accordance with the present invention is then processed through conventional electrode and wiring formation to form completed devices.
REFERENCES:
patent: 4978626 (1990-12-01), Poon et al.
patent: 5032530 (1991-07-01), Lowrey et al.
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5413945 (1995-05-01), Chien et al.
patent: 5585295 (1996-12-01), Wu
Fletcher Yoder & Van Someren
Lytle Craig P.
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