Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-27
2002-08-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06437411
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods for manufacturing the same, and more particularly, to semiconductor devices having metal silicide conductive layers, semiconductor devices having contact plugs self-aligned with a lower structure which is comprised of the conductive layers, and a method for manufacturing the semiconductor devices.
2. Description of the Related Art
As the integration density of semiconductor devices continues to increase, distance from contact holes that connect lower and upper interconnection layers to surrounding interconnections, decreases with an increase in the aspect ratio of the contact holes. Thus, highly integrated semiconductor devices adopting a multilayered interconnection structure require more accurate and strict processing conditions in contact hole formation by using photolithography. In particular, in manufacturing semiconductor devices having a design rule of 0.25 &mgr;m or less, current lithography techniques are not sufficient to reproducibly perform desirable processes with the same accuracy.
In order to overcome limitations of photolithography in the formation of contact holes, a self-alignment technique has been suggested for forming contact holes. For example, a self-alignment technique has suggested nitride spacers be used as an etch stop layer in the formation of self-aligned contact holes.
In the conventional self-alignment technique, first a lower structure, for example, a conductive layer such as a gate electrode having a rectangular section, is formed on a semiconductor substrate via patterning by a general photolithography process, and then a layer of nitride is deposited on the entire surface of the conductive layer. Then, an etchback process is carried out on the resulting structure so as to form nitride spacers, and then interlayer dielectric (ILD) oxide films are formed thereon. Thereafter, a photoresist pattern is formed on the ILD films for exposing contact holes, and the exposed ILD films are etched to form self-aligned contact holes.
In the conventional self-aligned contact hole formation, the ILD films are etched with a high selectivity with respect to the nitride spacers to form the contact holes. During the etching process, carbon rich carbon fluoride gases capable of producing a large amount of polymer, for example, C
4
F
8
or C
5
F
8
, are used so as to increase the selectivity.
However, if the etching conditions are determined to increase selectivity, the amount of polymer produced by the etching increases, so that the etching process may be interrupted, resulting in incomplete contact holes. Meanwhile, when the selectivity between the ILD films and the nitride spacers is decreased, complete contact holes can be formed without the interrupt due to the polymer. However, when the selectivity is low, the nitride spacers may be etched together with the ILD films during the etching process. Accordingly, the width of the remaining nitride spacers is too small to secure a desired insulation length from the sidewalls of conductive layers. Thus, it is prone to cause short between self-aligned contacts in the contact holes and the conductive layers.
In fabrication of highly integrated semiconductor devices having a design rule of 0.25 &mgr;m or less, when forming self-aligned contact holes over conductive layers such as gate electrodes or bit lines, which have an etch stop layer such as a nitride layer on the sidewalls thereof, an insulation thickness margin between the conductive layers and self-aligned contacts in the contact holes is not sufficient. A possible solution for overcoming this problem may be to lower the selectivity between ILD films and the etch stop layer in the self-aligned contact hole formation. However, the etch stop layer itself is removed or damaged with the low selectivity, so that it is difficult even to get a minimum insulation width at the edges of the conductive layer, increasing the possibility that the edges of the conductive layer directly be exposed to the contact holes.
Thus, in the self-aligned contact formation for manufacturing highly integrated semiconductor devices, the process margin is small even under optimal processing conditions, and thus it is difficult to reproducibly produce devices with the same accuracy.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide semiconductor devices allowing an increased process margin, in which a desired insulation length between a lower conductive layer and self-aligned contacts can be ensured in self-aligned contact hole formation for manufacturing highly integrated semiconductor devices.
It is another object of the present invention to provide semiconductor devices having contact plugs self-aligned with a lower structure having the above configuration.
It is still another object of the present invention to provide methods for manufacturing the semiconductor devices.
In an embodiment, the present invention provides a semiconductor device comprising: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.
Preferably, the semiconductor device further comprises contact plugs filling self-aligned contact holes in a self-aligning manner with the gate structures, the self-aligned contact holes exposing both the first insulation spacers and the active regions of the semiconductor device.
Preferably, the semiconductor device further comprises: a specific circuit having a predetermined function formed on the semiconductor substrate; a redundant circuit formed with the same function as that of the specific circuit on the semiconductor substrate; and a fuse formed with the same structure as that of the gate structures on the first insulation layer, the fuse being melted and removed for replacing a defective circuit with the redundant circuit.
Preferably, the semiconductor device further comprises: a planarized first interlayer dielectric (ILD) film pattern formed on the second insulation layer; bit lines formed on the first ILD film pattern; and a third insulation layer formed to cover the top surface of the bit lines, wherein the bit lines comprise conductive patterns and the upper edges of the conductive patterns are chamfered.
The semiconductor device may further comprise second insulation spacers on the sidewalls of the bit lines and on the sidewalls of the third insulation layer.
Preferably, the semiconductor device further comprises: a second ILD film pattern on the third insulation layer; and contact plugs filling self-aligned contact holes in a self-aligning manner with the bit lines, the self-aligned contact holes exposing both the second insulation spacers and an active region of the semiconductor device.
Preferably, the semiconductor device further comprises: a second ILD film pattern on the third insulation layer; and contact plugs filling self-aligned contact holes in a self-aligning manner with the gate structures and the bit lines, the self-aligned contact holes exposing both the first and second insulation spacers and an active region of the semiconductor device.
In another embodiment, the present invention provides a semiconductor device comprising: an ILD film pattern formed on a semiconductor substrate; bit lines formed on the ILD film pattern, the bit lines comprising conductive patterns and the upper edges of the conductive patterns being chamfered; and an insulation layer formed with a first width W on
Choi Chang-won
Choi Ji-hwan
Chung Dae-hyuk
Kim Bum-su
Kim Woo-sik
Myers Bigel & Sibley & Sajovec
Prenty Mark V.
Samsung Electronics Co,. Ltd.
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