Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-05-19
2002-02-12
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S204000, C365S149000, C365S189090
Reexamination Certificate
active
06347058
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a sense amplifier, typically as part of a DRAM (Dynamic Random Access Memory) array, having a transiently higher overdrive voltage for increased sensing speed provided by a capacitive charge source, and bitline voltage regulation during sensing.
DRAM arrays are memory devices widely used in a variety of computer-related applications. In many DRAM architectures, the access speed of a DRAM is directly tied to the speed of the transition of complementary bitline pairs from an equalized, pre-charged voltage level to final (within a given sensing cycle) high and low levels, and is an important performance parameter for a DRAM. Typically, the faster the access speed of a DRAM, the more useful and commercially popular it is as a product. Accordingly, much research and development is devoted to increasing this speed of transition, also referred to as the sensing speed or signal development speed.
FIG. 1
shows an example of a known circuit which is typically a basic component of a DRAM. Sense amplifiers
104
and
105
connect complementary bitline pairs BLA, /BLA and BLB, /BLB, respectively, which are connected to memory cells
100
-
103
. To read from/write to selected memory cells, a memory cell address is input to row/column decoders (not shown) which generate signals to activate a selected wordline and bitline corresponding to the address. In a read operation, the selected bitline and its complement output a small differential voltage value representing a logic “0” or “1” in response to the signals. The sense amplifiers amplify the differential voltage value to a full logic level for output to the required application.
FIG. 2
shows a timing diagram (time vs. voltage) corresponding to a read by the circuit of FIG.
1
. In particular, the curves labeled BLA and /BLA represent the voltage levels acquired, respectively, by bitlines BLA and /BLA during a sensing and amplifying period initiated in response to a wordline, WLA, being selected as described above. The rate at which the curves BLA and /BLA rise or fall from a pre-charged, equalized state (½ VBLH), to a desired final voltage (VBLH) for the high-going bitline, and a voltage at or near ground for the low-going bitline, represents a sensing or signal development speed which it is desirable to optimize as described above.
In
FIG. 2
, more particularly, a DRAM access is triggered by the /RAS (Row Address Strobe complement) signal going low. In response, the EQL signal goes low, ending a pre-charged condition for the bitlines and the SLP and SLN signal lines at ½ VBLH, maintained by equalizing devices
106
. As the selected wordline WLA goes high, the access transistor of the memory cell
100
begins to conduct, and the storage capacitor begins to charge-share with BLA. The capacitor has been preset either to a low voltage (near ground), typically representing a logic “0”, or a high voltage (near VBLH) typically representing a logic “1”.
After a small differential voltage &Dgr;v has developed between BLA and /BLA as a result of the charge-sharing, a sensing operation is initiated by driving the SEP signal low and the SEN signal high to activate the sense amplifier
104
. This connects the SLP line with a voltage at the VBLH level and the SLN line with a voltage at or near ground.
As is understood in the art, the PFETs and NFETs of the sense amplifier conduct in a sequence corresponding to whether the bitline connected to the memory cell is high-going or low-going with respect to its complementary bitline, as a result of charge-sharing with the memory cell. Thus, as the SLP line is pulled toward VBLH from ½ VBLH, the high-going bitline is pulled toward VBLH, and as the SLN line is pulled toward ground from ½ VBLH, the low-going bitline is pulled toward ground as shown on the BLA, /BLA time axis. At a point after the transistors of the sense amplifier begin to conduct, the sense amplifier is said to have “set” or “latched”.
It is recognized in the art that one way to increase the speed of transition of the bitline voltages is to provide a higher “overdrive” voltage to the transistors of the sense amplifier via the SLP and SLN lines. “Overdrive” as used herein refers to an amount of voltage in excess of a gate-to-source threshold voltage of a transistor. For example, if a voltage of 1 volt is applied gate-to-source to a transistor having a gate-to-source threshold voltage of ½ volt, ½ volt of the applied voltage is overdrive voltage. As is known, the amount of overdrive voltage applied to a transistor determines the amount of current the transistor will supply. In a saturated mode in which the transistors of the sense amplifier operate during sensing, the greater the overdrive voltage applied, the greater the current delivered by the transistors. Because the transistors are charging and discharging the bitlines, the greater current enables a faster voltage transition on the bitlines.
Providing a higher overdrive voltage as described above has posed problems as “technology scaling” has occurred in DRAM designs. Technology scaling refers to making all DRAM features smaller so as to pack bits more densely on a silicon chip. However, voltages must be scaled commensurately with feature size; voltages that are too high tend to break down the thinner films and insulators of the scaled-down structures. DRAMs also usually include wear-out mechanisms that, when scaled smaller, wear out earlier at lower voltages. Therefore, voltages in general cannot be kept at a consistently higher level.
Accordingly, techniques have been proposed for applying higher overdrive voltage transiently during sensing to increase sensing speed, but otherwise keeping voltage levels at a scale better suited for smaller DRAM structures. However, these techniques do not address the need for stabilizing and precisely controlling the final voltage of the overdriven bitline in an end period of a sensing cycle.
Such stability and precise control are highly desirable for several reasons. For instance, typically of the art, the read operation described above is “destructive”; i.e., the charge of the memory cell is disturbed by charge-sharing with the bitlines, and consequently the charge must be refreshed after each read operation by a “write-back” operation, which re-impresses the final bitline voltage on the memory cell. If the correct final bitline-high voltage is undershot, less than the correct amount of charge for representing a data “1” will be written back to the memory cell during the refresh stage. On the other hand, if the correct final bitline-high voltage is overshot, the reliability of the cell is compromised because write-back will place too high an electric field across its oxide.
Control of final bitline voltage is also important because of factors present in a typical DRAM array which tend to cause unpredictable and undesired variations in the final bitline voltage. For instance, variations in the DRAM fabrication process such as image size and oxide thickness will cause key components of bitline capacitance to vary from chip to chip. These key components, for example, include the cell device drain junction and gate overlap capacitance plus wiring capacitance. The variations of these components of bitline capacitance present problems when charge sharing is utilized to set the bitline high voltage level after sensing.
The data state of the DRAM cells also affects the total charge that must be supplied in sensing, and consequently affects the final bitline voltage. This can be seen by observing that the charge level of the high-going bitline of a bitline pair may start from either of two points once sensing begins. One point is the equalized, pre-charged level (½ VBLH in the case described above), and the other is the equalized, pre-charged level, plus a small charge increment developed from charge-sharing with a memory cell storing a “1”, as illustrated by the positive &Dgr;v shown in the example of FIG.
2
. Charging up the high-going bitline from
Houghton Russell J.
Miller Christopher P.
Auduong Gene N.
Connolly Bove Lodge & Hutz
Nelms David
Walsh, Esquire Robert
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