Nonvolatile memory device and method for fabricating the same

Details Nonvolatile memory device and method for fabricating the same Nonvolatile memory device and method for fabricating the same

2000-11-14

2002-06-25

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000, C438S279000, C438S129000, C438S599000

Reexamination Certificate

active

06410390

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device and method for fabricating the same which is capable of reducing the size of a chip and simplifying the process for forming a common source line.
2. Background of the Related Art
In general, semiconductor memory devices are mainly divided into two main groups, i.e., a volatile memory device which is capable of erasing the stored data and then restoring new data, and a nonvolatile memory device which permanently reserves the stored data.
The volatile memory device includes a RAM capable of reading and writing of data and the nonvolatile memory device includes a ROM(Read Only Memory), EPROM(Erasable Programmable ROM) and EEPROM(Electrically Erasable Programmable ROM).
In the nonvolatile memory device, the ROM is not possible to reprogram once it stores the data. The EPROM and EEPROM is possible to erase the stored data and then reprogram. EPROM and EEPROM are the same in operation of programming the data, but different in methods of erasing the stored data. Specifically, the EPROM erases the stored data using ultraviolet and EEPROM erases the stored data electrically.
When a plurality of the nonvolatile memory devices are arranged in a form of matrix, sources of the nonvolatile memory devices can be connected for increasing the integration. Accordingly, methods for connecting sources of the nonvolatile memory devices have been studied.
With reference to the accompanying drawings, a related art nonvolatile memory device and a method for fabricating the same will be described.
FIG. 1
is a plan view showing a cell array of a related art nonvolatile memory device,
FIG. 2
a
is sectional view showing a structure of the related art nonvolatile memory device taken along the line I—I in
FIG. 1
, and
FIG. 2
b
is a sectional view showing a structure of the related art nonvolatile memory device taken along the line II—II in FIG.
1
.
As shown in
FIGS. 1
,
2
a
and
2
b
, the related art nonvolatile memory device includes a semiconductor substrate
10
defining a plurality of active regions and a field region. A field oxide film
11
is formed on the field region. The active regions are aligned in one direction.
A plurality of tunneling oxide films
12
and floating gates
13
are deposited on each of the active regions in a predetermined pattern. Inter-poly dielectric layers
14
and control gate lines are deposited in a direction perpendicular to the active regions to cover the floating gates
13
.
The control gate lines are formed to be bent outwardly, because an area for forming a contact wire in a common source ion injection region which is to be formed at a later step requires a greater margin.
The tunneling oxide films
12
, floating gates
13
, inter-poly dielectric layers
14
and control gate lines
15
are provided with sidewalls
19
a
at both sides thereof. The sidewalls
19
a
at the inner sides of the control gate lines
15
in which the common source ion injection region is to be formed are partially removed.
In a state that pairs each consisting of two, i.e., first and second control gate lines
15
are aligned, drain regions are formed in the semiconductor substrate
10
outside of the pairs of the first and second control gate lines
15
. Also, a common source ion injection region
21
is formed in the semiconductor substrate
10
between the first and second control gate lines
15
.
Referring to
FIG. 1
, the reference numerals
22
and
23
denote a drain wire and a source wire, respectively. The drain wire
22
is aligned with the active region to connect the drain regions on a same active region. The source wire
23
is aligned with the active region to connect the common source ion injection regions
21
.
Referring to
FIGS. 3
a
and
4
a
, the process for manufacturing the above-explained related art nonvolatile memory device will be described.
A field oxide film
11
is formed on the field region of the semiconductor substrate
10
defining the active regions and the field region. A first oxide film and a first polysilicon layer are deposited in a direction aligned with each active region of the semiconductor substrate
10
.
A second oxide film and a second polysilicon layer are successively deposited on the entire surface of the semiconductor substrate
10
using a chemical vapor deposition (CVD). A photo-sensitive film is coated on the second polysilicon layer and then patterned in one direction perpendicular to the active regions. The second polysilicon layer, the second oxide film, the first polysilicon layer and the first oxide film are successively anisotropic-etched, using the patterned photo-sensitive film as a mask.
By the above steps, as shown in
FIGS. 3
a
and
4
a
, the tunneling oxide film
12
and the floating gate
13
are formed on one portion of the active region of the semiconductor substrate
10
in a predetermined pattern. Also, an inter-poly dielectric layer
14
and a control gate line
15
are formed in one direction perpendicular to the active region to cover the floating gate
13
. Then, the photo-sensitive film is removed.
Then, as shown in
FIGS. 3
b
and
4
b
, a first photo-sensitive film
16
is deposited on the entire surface of the semiconductor substrate
10
. The first photo-sensitive film
16
is selectively patterned by exposing and developing process, so as to expose a portion of the active region of the semiconductor substrate
10
in which a drain region is to be formed.
First conductive ions are injected into the portion which is to be a drain region, using the patterned first photo-sensitive film as a mask, thereby forming a drain region
18
.
By tilt ion injection method, second conductive ions are injected into a bottom portion of the floating gate
13
adjacent to the drain region, to form a halo ion region
17
. Then, the first photo-sensitive film
16
is removed.
As shown in
FIGS. 3
c
and
4
c
, an insulating layer
19
is formed over the entire surface of the semiconductor substrate
10
.
As shown in
FIGS. 3
d
and
4
d
, the insulating layer
19
is anisotropic-etched to form sidewalls
19
a
at both sides of the tunneling oxide film
12
, the floating gate
13
, the inter-poly dielectric layer
14
and the control gate line
15
.
As shown in
FIGS. 3
e
and
4
e
, a second photo-sensitive film
20
is coated on the entire surface of the semiconductor substrate
10
. Then, the second photo-sensitive film
20
is selectively patterned by exposing and developing process, so as to expose the field oxide film
11
and the active regions between the control gate lines.
The field oxide film
11
and the sidewalls
19
a
are anisotropic-etched to expose the semiconductor substrate
10
between the control gate lines
15
using the patterned second photo-sensitive film
20
as a mask. At this time, there occurs a problem that the surface of the active region of the semiconductor substrate
10
is etched.
The process for etching the field oxide film
11
using the second photo-sensitive film
20
and sidewall
19
a
as a mask in order to form a common source ion injection region is referred to as a self-align source dry-etching process.
The first conductive ions are injected into the exposed portion of the semiconductor substrate
10
between the control gate lines
15
to form a common source ion injection region
21
in one direction between the control gate lines
15
.
However, the related art nonvolatile memory device and the method for fabricating the same has the following problems.
First, when the field oxide film is removed, i.e., when the self-align source dry-etching process is performed in order to form a common source ion injection region, the semiconductor substrate may be lost to reduce the reliance on the operation of the semiconductor device.
Second, if ions are injected into the lost portion of the semiconductor substrate after the self-align source dry-etching process, it is not easy to control the concentration of the source re

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