Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-08
2002-11-26
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S223000, C438S224000, C438S227000, C438S228000, C438S257000
Reexamination Certificate
active
06486013
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to an isolation technology in semiconductor devices such as a DRAM, an EEPROM, etc.
With further miniaturization of elements in semiconductor devices, an isolation method has become one of the critical problems to be overcome. A method known as local oxidation of silicon (LOCOS) has been widely used as the isolation method. When isolation is carried out by this LOCOS method, however, bird's beaks develop and limit the area of forming elements such as transistors. Therefore, this method cannot easily satisfy the higher integration density of semiconductor devices required recently. A so-called “field-shield isolation” method, which isolates elements by a MOS structure formed on a semiconductor substrate, has been proposed as an isolation method which does not generate the bird's beaks.
Generally, the field-shield isolation structure has a MOS structure in which shield gate electrodes made of a polycrystalline silicon (poly-silicon) film are formed over a silicon substrate through a shield gate oxide film. This shield gate electrode is always kept at a constant potential of 0 V, as it is grounded (GND) through a connection conductor when the silicon substrate (or a well region) has a P type conductivity. When the silicon substrate (or the well region) has an N type conductivity, the shield gate electrode is always kept at a predetermined potential (a power source potential Vcc [V], for example).
Because the formation of a channel of a parasitic MOS transistor on the surface of the silicon substrate immediately below the shield gate electrode can be prevented, adjacent elements such as transistors can be electrically isolated from one another. According to this field-shield isolation, ion implantation for forming the channel stopper which has been necessary for the LOCOS is not necessary. In consequence, a narrow channel effect of the transistor can be reduced and the substrate concentration can be lowered the junction capacitance formed inside the substrate-becomes small, and the operation speed of the transistor can be improved.
JP-A-61-75555 (laid-open on Apr. 17, 1986 and corresponding to U.S. Ser. No. 626,572 filed Jul. 2, 1984 with U.S. PTO) discloses a semiconductor device employing a field-shield structure or field oxide film for isolation between elements.
JP-A-63-305548 (laid-open on Dec. 13, 1988) discloses a semiconductor device in which a field oxide film is formed on an n-type semiconductor region and a field-shield structure is formed on a p-type semiconductor region.
SUMMARY OF THE INVENTION
As a result of researches and investigations conducted by the present inventors, it has been found with the field-shield isolation structure that inconveniences are encountered when it is required to form wells to be fixed or kept at different potentials for the purpose of forming a circuit such as a CMOS circuit, as will be described below.
Generally, in a CMOS circuit, a P-type well in which an N-type MOS transistor is formed is kept at the ground potential, while an N-type well in which a P-type MOS transistor is formed is kept at a power supply potential. Thus, a shield gate electrode for isolation of the N-type MOS transistor in the P-type well must be kept at the ground potential, and a shield gate electrode for isolation of the P-type MOS transistor in the N-type well must be kept at the power supply potential for isolation of the transistor elements. Therefore, it is impossible to directly connect to either a shield electrode for the N-type well or a shield electrode for the P-type well a shield gate electrode which serves to isolate elements near a junction between the P-type well and the N-type well, one in the P-type well and the other in the N-type well. This necessitates formation of an isolating active region at the junction of the N-type and P-type wells. As a result, direct connection of the gates of the N-type and P-type MOS transistors with a poly-silicon becomes impossible, and additional connection conductors have to be provided at a higher level for the connection of the gates of the transistors.
Due to the above-mentioned structural limitations, a large area is needed to impede a high integration of the circuit. Further reliability of a multi-layer connection structure needs to be ensured, which will make the production cost higher.
It is therefore an object of the present invention to provide a semiconductor device having an isolation structure which is useful for integrating semiconductor elements or circuit elements at a high integration density and reducing a chip area, and a method of manufacturing such a semiconductor device.
It is another object of the present invention to provide a semiconductor device in which two element formation regions or semiconductor regions having different conductivity types can be isolated from each other by an isolation. structure having a smaller size than those of the prior art devices, and a method of manufacturing such a semiconductor device.
It is still another object of the present invention to provide a semiconductor device in which electrical connection is possible between elements formed at the boundary between two element formation regions or semiconductor regions having different conductivity types by an integrated (single) connection conductor, and a method of manufacturing such a semiconductor device.
According to one aspect of the present invention, a field oxide film is formed at a main surface of a semiconductor substrate, the field oxide film having an inner'surface located within the semiconductor substrate, and a junction formed between two semiconductor regions of different conductivity types defined in the semiconductor substrate terminates at the inner surface of the field oxide film. By this structure, the semiconductor regions of different conductivity types are isolated from each others. This makes it possible to form a conductor extending on the isolating field oxide film for making electrical connection between circuit elements in the isolated semiconductor regions.
According to another aspect of the present invention, a semiconductor device has a first well region of a first conductivity type and a second well region of a second conductivity type, that are fixed at mutually different potentials. These are formed adjacent to each other in a surface portion of a semiconductor region. A plurality of MOS transistors, each having source/drain regions of an opposite conductivity type to that of each well, are formed in at least one of the first and second regions. These MOS transistors are electrically isolated from one another by a field-shield isolation structure and the first and second regions are electrically isolated from each other by a first field oxide film.
According to still another aspect of the present invention, in a semiconductor device including a plurality of well regions formed in a surface portion of a semiconductor substrate, these well regions are electrically isolated from each other and from the semiconductor substrate by a field oxide film. The isolation of other elements is attained by field-shield isolation structures.
REFERENCES:
patent: 5067000 (1991-11-01), Eimori et al.
patent: 5541130 (1996-07-01), Ogura et al.
patent: 56-70644 (1981-06-01), None
patent: 61-75555 (1986-04-01), None
patent: 63-305548 (1988-12-01), None
Eguchi Kohei
Hazama Katsuki
Kawasaki Atsushi
Sugaya Fumitaka
Connolly Bove & Lodge & Hutz LLP
Guerrero Maria
Meier Stephen D.
Nippon Steel Corporation
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