Semiconductor memory device with reduced interference...

Details Semiconductor memory device with reduced interference... Semiconductor memory device with reduced interference...

2001-10-02

2002-08-27

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230030

Reexamination Certificate

active

06442087

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device, and particularly a structure for rapidly and accurately reading out data. More particularly, the invention relates to a structure for reducing interference between bit lines upon reading out of memory cell data in a semiconductor memory device.
2. Description of the Background Art
FIG. 17
schematically shows a whole structure of a conventional static semiconductor memory device. In
FIG. 17
, the semiconductor memory device includes a memory cell array MA having memory cells arranged in rows and columns.
FIG. 17
shows, by way of example, memory cells M
1
-M
8
arranged in two rows and four columns. Word lines WL are arranged corresponding to the memory cell rows, respectively, and bit line pairs are arranged corresponding to the memory cell columns, respectively. In
FIG. 17
there are shown, as a representative, a word line WL
1
arranged corresponding to the row of memory cells M
1
-M
4
and a word line WL
2
arranged corresponding to the row of memory cells M
5
-M
8
. As for the bit line pairs, there are shown bit lines B
1
and /B
1
-B
4
and /B
4
in FIG.
17
.
The semiconductor memory device further includes: a bit line precharge circuit
11
for precharging these bit lines B
1
and /B
1
to B
4
and /B
4
to a power supply voltage level in response to a clock signal T; a row decode circuit
14
operating in synchronization with clock signal T and decoding a row address signal X applied thereto to drive a word line corresponding to the addressed row to the selected state; a column decode circuit
5
for decoding column address signals Y
0
and Y
1
applied thereto to drive one of column select signals DY
1
-DY
4
selecting an addressed column to the selected state; a read/write circuit
6
operating in synchronization with clock signal T and reading and writing data in accordance with a write signal WE; and a multiplexer
2
for coupling a bit line pair corresponding to the selected column to read/write circuit
6
via internal data lines DL and /DL in accordance with column select signals DY
1
-DY
4
received from column decode circuit
5
.
Multiplexer
2
includes column select gates CG arranged corresponding to the respective memory cell columns. In
FIG. 17
, there are shown column select gates CG
1
-CG
4
arranged corresponding to bit lines B
1
and /B
1
to B
4
and /B
4
in four columns, and made conductive when corresponding column select signals DY
1
-DY
4
are active, respectively.
Bit line precharge circuit
11
includes bit line load circuits L
1
-L
4
arranged corresponding to bit line pairs B
1
and /B
1
to B
4
and /B
4
, respectively. Each of bit line load circuits L
1
-L
4
includes a P-channel MOS transistor P
1
for precharging a corresponding bit line B (B
1
-B
4
) to the power supply voltage level when turned on, and a P-channel MOS transistor P
2
for precharging a complementary bit line /B (/B
1
-/B
4
) to the power supply voltage level when turned on.
Each of column select gates CG
1
-CG
4
included in multiplexer
2
includes N-channel MOS transistors NI and N
2
, which are turned on, when corresponding column select signal DYi (i=1-4) is selected, to connect corresponding bit lines B and /B to internal data lines DL and /DL, respectively.
The static semiconductor memory device shown in
FIG. 17
is a clock synchronous semiconductor memory device, which performs selection of a row and a column as well as write/read of data in synchronization with clock signal T. When clock signal T is at L level, all bit line load circuits L
1
-L
4
are activated in bit line precharge circuit
11
, and bit lines B
1
and /B
1
to B
4
and /B
4
are precharged to power supply voltage VCC level by corresponding P-channel MOS transistors P
1
and P
2
. Row decode circuit
14
and column decode circuit
5
are inactive, and word lines WL
1
and WL
2
as well as column select signal DYi are in the unselected state.
When clock signal T attains H level, the memory select operation and access operation are performed. More specifically, row decode circuit
14
is activated to decode a row address signal X, for driving a word line WL (WL
1
or WL
2
) corresponding to the addressed row to the selected state. At the same time, column address signals Y
0
and Y
1
are applied, and column decode circuit
5
is activated in synchronization with the rising of clock signal T to perform the decoding of the column address, for driving one of column select signals DY
1
-DY
4
to the selected state in accordance with the result of decoding. Responsively, bit lines B and /B corresponding to the selected column are coupled to internal data lines DL and /DL, respectively.
In the data read operation, the voltages on bit lines B and /B precharged to the power supply voltage level, change in accordance with data stored in the selected memory cell, and a sense amplifier circuit included in read/write circuit
6
amplifies the voltage difference between the bit lines corresponding to this selected column to produce read data. In the data write operation, a write circuit included in read/write circuit
6
produces complementary internal write data in accordance with externally supplied write data, for transmission to bit lines B and /B corresponding to the selected column. In this data write operation, one of bit lines B and /B precharged to the power supply voltage level is driven to the ground voltage level in accordance with the internal write data.
In
FIG. 18A
, there is shown, by way of example, a structure of row decode circuit
14
shown in FIG.
17
. In
FIG. 18A
, row decode circuit
14
includes an inverter circuit
14
a
for inverting row address signal X, an AND circuit
14
b
receiving an output signal of inverter circuit
14
a
and clock signal T, and transmitting a word line drive signal onto word line WL
1
, and an AND circuit
14
c
receiving clock signal T and row address signal X, and transmitting a word line drive signal onto word line WL
2
.
Row decode circuit
14
shown in
FIG. 18A
includes an AND type decode circuit as a unit decode circuit. Word lines WL
2
and WL
1
are selectively designated in accordance with H and L levels of row address signal X. A decode operation of row decode circuit
14
shown in
FIG. 18A
will now be briefly described with reference to a timing chart of FIG.
18
B.
When clock signal T is at L level, the output signals of AND circuits
14
b
and
14
c
are at L level, and both word lines WL (WL
1
and WL
2
) are at L level. In
FIG. 18B
, externally applied row address signal X applied, for example, from a processor changes in synchronization with the falling of clock signal T.
When clock signal T rises to H level, AND circuits
14
b
and
14
c
are enabled, and one of word lines WL
1
and WL
2
is driven to the selected state in accordance with row address signal X. When row address signal X is at H level, AND circuit
14
c
transmits the word line drive signal onto word line WL
2
, and word line WL
2
is driven to the selected state. When row address signal X is at L level, AND circuit
14
b
activates the word line drive signal to drive word line WL
1
to the selected state. When clock signal T falls to L level, both of the output signals of AND circuits
14
b
and
14
c
attain L level, and the memory cell access cycle ends. Accordingly, word lines WL
1
and WL
2
attain the unselected state, and bit line precharge circuit
11
shown in
FIG. 17
precharges bit lines B and /B to the power supply voltage level.
FIG. 19
shows, by way of example, a structure of memory cells M
1
-M
8
shown in FIG.
17
.
FIG. 19
shows memory cell M
1
as a representative. These memory cells M
1
-M
8
have the same structure.
In
FIG. 19
, memory cell M
1
includes; a P-channel MOS (insulated gate type field effect) transistor TR
1
which is connected between a power supply node and a storage node SNA, and has a gate connected to a storage node SNB; a P-channel MOS transistor TR
2
which is connected between the power s

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