Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-04
2002-10-29
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S290000, C438S291000
Reexamination Certificate
active
06472278
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to field effect transistors and more particularly to very high dielectric constant gate field effect transistors.
BACKGROUND OF THE INVENTION
The pressure to continually scale down the size of semiconductors requires that thinner and thinner gates be used. The standard dielectric layer, SiO
2
, for semiconductor field effect transistor (FET) gates is becoming too thin to prevent excessive tunneling current. Higher dielectric constant (K) materials, such as Si
3
N
4
(K=7) and Ta
2
O
5
(K=20), are being investigated for some electrical applications. For example, high K materials have been used to form electrical components such as non-volatile memories, capacitors, and optical guided wave devices.
A FET consists of a gate insulator disposed over a semiconductor substrate, with a small amount of dopant placed into its surface using a threshold implant, and gate metal disposed over the gate insulator. The gate metal and the gate insulator are etched to form a gate structure and a self-aligned source/drain implant is used to form the source and drain of the device. By applying a potential to the gate metal, the gate insulator transmits charge to the semiconductor substrate and the semiconductor substrate is induced to become an n or p-type conductor under the gate insulator. This in turn makes the device laterally conductive or insulating, depending on the channel type of the semiconductor substrate and the threshold voltage of the FET, which is determined by the threshold implant under the gate insulator. A drawback in the manufacture of these devices is that the threshold implant takes time and must be controlled to a precise level. Another drawback in the manufacture of these devices is the need to implant the source and drain using a self-aligned implant on either side of the gate structure. These drawbacks result in higher production costs.
Accordingly, it would be advantageous if the need for the threshold implant were eliminated and if the threshold voltage of the FET were determined essentially by material parameters.
It is a purpose of the present invention to provide a new and improved FET and method of manufacture.
It is another purpose of the present invention to provide a new and improved FET in which gate leakage current and device capacitance are reduced.
It is a further purpose of the present invention to provide a new and improved FET in which the threshold voltage of the FET are determined essentially by material parameters.
It is a still further purpose of the present invention to provide a new and improved FET and method of manufacture in which the need for a threshold implant is eliminated.
It is another purpose of the present invention to provide a new and improved FET and method of manufacture in which the need for self-aligned source/drain implants is eliminated.
It is still another purpose of the present invention to provide a new and improved enhancement mode FET and method of manufacture using a depletion mode-type constant implant between and including the source and the drain.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in a method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. Preferably the dielectric constant of the insulator layer is at least 25. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.
REFERENCES:
patent: 5436490 (1995-07-01), Nakamura
patent: 5686151 (1997-11-01), Imai et al.
patent: 5851844 (1998-12-01), Ooms et al.
patent: 5962897 (1999-10-01), Takemura et al.
patent: 5973379 (1999-10-01), Ooms et al.
patent: 5986301 (1999-11-01), Fukushima et al.
Hallmark Jerald A.
Marshall Daniel S.
Ooms William J.
Wang Yang
Dang Trung
Gilmore Douglas W.
Koch William E.
Motorola Inc.
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