Method of making a single transistor non-volatile memory device

Details Method of making a single transistor non-volatile memory device Method of making a single transistor non-volatile memory device

2001-02-12

2002-12-17

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S596000

Reexamination Certificate

active

06495420

ABSTRACT:

The present invention relates to a semiconductor device, and more specifically, to a method of fabricating nonvolatile memories.
BACKGROUND OF THE INVENTION
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMS. Different types of devices have been developed for specific applications requirements in each of these segments. These parts have been developed with a focus on the high endurance and high speed requirements. In such device, electrical alterability is achieved by Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-thin dielectric interface and into the oxide conduction band. Typically, the thin dielectric layer is composed of silicon dioxide and the thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide and remain trapped there since the materials are high quality insulators.
Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistor are used for the bit lines. See “A New Self-Aligned Planar Cell for Ultra High Density EPROMs, A. T. Mitchellx, IEDM, Tech. pp. 548-553, 1987”. Bergemont proposed another cell array for high density flash EEPROM, which can be seen in “NOR Virtual Ground (NVG)—A New Scaling Concept for Very High Density FLASH EEPROM and its Implemntation in a 0.5 &mgr;m Process, A Bergemont, IEEE, pp. 15-18, 1993”. This cell structure is introduced for scaling down the size of the devices to fabricate high density EEPROMs. Another prior art that relates to the field is the U.S. Pat. No. 4,203,158.
However, most of such device includes a floating gate transistor and a separate select transistor for each storage site. These structure occupies larger area, it does not meet the trend of the technology. One prior art discloses single transistor nonvolatile device. Please refer to U.S. Pat. No. 5,029,130 to Bing Yeh, which assigned to Silicon Storage Technology.
SUMMARY OF THE INVENTION
The object of the present invention is to form one single transistor nonvolatile memory which inlcudes a sharp corner to improve the efficiency of electron injection.
A method for manufacturing one single transistor nonvolatile memory is disclosed. The method comprises forming a first oxide layer as a sacrificial dielectric layer on a semiconductor substrate. A nitride layer is formed on the sacrificial dielectric layer. Then, the sacrificial dielectric layer and the nitride layer are patterned to form an opening therein, thereby exposing a portion of the semiconductor substrate. Next, a second oxide layer is formed on the nitride layer and along a surface of the opening. An etching is performed to etch the second oxide layer to form side wall spacers on side walls of the opening. Then, a gate dielectric layer is formed on the exposed semiconductor substrate. A first polysilicon layer is deposited on the nitride layer. Subsequently, the first polysilicon layer is polished by CMP and the nitride layer, the spacers and the sacrificial dielectric layer are stripped. A tunneling dielectric layer and a control gate are respectively formed on a surface of the floating gate.


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