Use of a hard mask in the manufacture of a semiconductor device

Details Use of a hard mask in the manufacture of a semiconductor device Use of a hard mask in the manufacture of a semiconductor device

2000-10-06

2002-12-10

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000, C438S232000

Reexamination Certificate

active

06492218

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method of a semiconductor device, in particular, a shallow extension diffusion layer forming method of a CMOS (complementary metal oxide semiconductor).
DESCRIPTION OF THE RELATED ART
Conventionally, in a shallow extension diffusion layer forming process of a CMOS, when about 0.5 keV is applied to implant boron ions, its projecting range of impurities (boron ions) is about 2 to 3 nm. And, in case that a native oxide film (1 to 1.5 nm) forming at the time of cleaning exists on a silicon substrate, a large number of boron ions are implanted to this native oxide film. Consequently, the number of impurities implanting to the silicon substrate becomes small.
And also it is recognized that the influence of transient enhanced diffusion appears caused by the existence of the native oxide film on the silicon substrate at the time of RTA (rapid thermal annealing). Therefore, in order to make the junction part shallow, it is desirable that the surface of the silicon substrate is exposed at the time of annealing without the native oxide film. The transient enhanced diffusion can be restrained by removing the native oxide film by applying an HF (hydrogen fluoride) treatment right before the RTA. However, at this time, the impurities implanted in the native oxide film of the silicon substrate are also removed.
FIG. 1
is a graph showing characteristics at the time of removing the native oxide film in a process between the ion implantation and the RTA. As shown in
FIG. 1
, the large amount of dopant loss occurs, when the HF treatment is applied before the RTA. Therefore, it is necessary that the native oxide film must be removed before the time of the ion implantation.
And when the surface of the silicon substrate is oxidized at a process, such as a resist removing process, between the ion implantation process and the RTA process, the dopant loss also occurs. Therefore, it is necessary to omit processes in which the surface of the silicon substrate is liable to be oxidized, such as the resist removing process, after the ion implantation process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a manufacturing method of a semiconductor device, in which a native oxide film is removed before the time of ion implantation, and also processes in which the surface of the silicon substrate is liable to be oxidized, such as a resist removing process, can be omitted after the ion implantation.
According to the present invention for achieving the object mentioned above, in a manufacturing method of a semiconductor device, at a shallow extension diffusion layer forming process for manufacturing a CMOS (complementary metal oxide semiconductor), when ion implantation is performed to a pMOS region, a hard mask to prevent a dopant from the ion implantation to an nMOS region is used, and the hard mask is also used as a mask to restrain out diffusion of a dopant of the nMOS region.
According to the present invention, there is provided a manufacturing method of a semiconductor device at a shallow extension diffusion layer forming process for manufacturing a CMOS. At this manufacturing method, an HF treatment process for removing a native oxide film on a silicon substrate is performed before an ion implantation process for extension to a pMOS region is performed, and the ion implantation process is performed by using a hard mask made of at least an oxide film on an nMOS region, and before the ion implantation process is performed, a thin film side wall is formed on only a gate electrode of the pMOS region, and before an impurities activation RTA treatment to the pMOS region, a cap film being a hard mask to prevent out diffusion of impurities of the nMOS region is formed at the nMOS region, and the surface of the silicon substrate is exposed without a native oxide film at the pMOS region, in order to restrain transient enhanced diffusion.
According to the present invention, at the shallow extension diffusion layer forming process at the CMOS, in order to omit processes that cause a dopant loss and transient enhanced diffusion between an ion implantation process to a pMOS region and an RTA process, a hard mask is used at the time of the ion implantation. And the hard mask is also used as a mask to restrain the out diffusion of the dopant of the nMOS. Therefore, a dopant loss between the ion implantation to the pMOS region and the RTA process is restrained and also the transient enhanced diffusion can be restrained. With this, the native oxide film can be removed before the time of the ion implantation, and a process that the surface of the silicon substrate is liable to be oxidize, such as a resist removing process, can be omitted after the ion implantation.


REFERENCES:
patent: 5741725 (1998-04-01), Inoue et al.
patent: 5864161 (1999-01-01), Mitani et al.
patent: 5940699 (1999-08-01), Sumi et al.
patent: 09167804 (1997-06-01), None

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