Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-17
2002-02-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S228000, C438S305000
Reexamination Certificate
active
06350641
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Present invention relates to a fabrication method for a high voltage device, and especially relates to increasing the depth of N-type lightly doping in a high voltage device.
2. Description of the Prior Art
In the field of metal oxide semiconductors, the length of the channel will become shorter as the size of the device decreases, and the operation time will become shorter too. However, the length of channel of MOSFET cannot be shortened indefinitely, or else the short channel of device will result in some problems called “the short channel effect”.
If we maintain the design parameters of a device, only reducing the channel length of MOS device, the depletion region in source/drain region produced during process will overlap the channel. As the length of the channel is shortened the channel gets closer to the depletion region width of the source/drain region of device, and the overlap between the source/drain region of device and the depletion region will become wider. The short channel will make control of the gate to channel worse. Besides, a partial channel be shared by the depletion region of source/drain region, so sub-threshold current will increase, and threshold voltage of device will be lowered.
If we further reduce the channel of the MOSFET to about 0.15 &mgr;m, PN junction between the channel and source/drain region of the device will be affected. Besides, this will increase the subthreshold current resulting from more electrons being injected into the channel from the source region. This will make the MOS become open or almost open while the gate voltage of NOMS is zero, and when advanced, it will lose the control to the MOS of the gate.
If the channel of MOSFET is reduced without lowering the operation voltage at the same time, this will enhance the electric field of the channel. The electric field near the drain region is stronger. This will reduce in electron/hole pair for the impact effect of electrons gained enough energy near the drain region, and the electron/hole pair will spoil the device. This is the “hot carrier effect.” The hot carrier effect of electrons is more serious than the one of the hole, so the NMOSFET will suffer more problems.
Hot carrier effect becomes more serious as the channel of the MOSFET is further shortened. There are many methods to resolve this issue, and one of them is to lower the operation voltage of the MOSFET. If for example, the voltage is lowered from 5V to 2.5V, this will permit the electric field to become too weak to result in a hot carrier, and the hot carrier effect will be lessened effectively. Another method to lessen the hot carrier effect the so-called “lightly doped drain (LDD)”. In such a way, we add a low concentration N-type region into portion region of the source/drain region of the MOSFET, and the region is near the channel of the device.
Some problem will be encountered when the high voltage (8~1000V) device is integrated in deep submicron process. In the high voltage NMOSFET device process, N-type LDD is used to lessen the hot carrier effect of high voltage devices and to increase breakdown voltage. However, in the traditional process, the N-type lightly doped drain step occurred after the poly step, thus the source/drain region is executed anneal only once and enough doping depth cannot be acquired. Besides, if we apply a multi-step high energy N-type lightly doped, this will effect throughput and cost.
Based on the former statement, a better integration process is needed to increase the anneal turns in identical process and then improve the profile and depth of N-type lightly doped region.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for solving problems in a traditional high voltage device process.
It is another object of this invention to lessen the hot carrier effect of high voltage device and to increase operating voltage of a high voltage device.
It is a further object of this invention to form a better N-type lightly doped profile and depth to improve throughout and cost.
A method for fabricating a high voltage device with double diffusion structures provides a pad oxide layer on a silicon substrate. A silicon nitride layer is formed and patterned to expose isolation regions. A first mask covers the partial isolation regions spaced from the silicon nitride layer. A well region is formed underlay the silicon nitride layer. A second mask covers the partial isolation regions spaced from the silicon nitride layer and the partial silicon nitride layer. First doped regions are formed underlay the partial silicon nitride layer. Then the isolation regions are formed partially on the first doped regions. Next, a third mask covers the pad oxide layer and the partial isolation regions and second doped regions are formed spaced from the first doped regions and below the isolation regions. A gate is formed and located between the first doped regions and a spacer on a side-wall thereof. Third doped regions are formed in the first doped regions.
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Niebling John F.
Powell Goldstein Frazer & Murphy LLP
Roman Angel
United Microelectronics Corp.
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