Static information storage and retrieval – Read/write circuit – Multiplexing
Reexamination Certificate
2002-02-06
2002-11-19
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Multiplexing
C365S230020, C365S238500
Reexamination Certificate
active
06483753
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits and more particularly to a computer system having multiple memory access devices and a shared memory space.
BACKGROUND OF THE INVENTION
In a computer system having multiple memory access devices, a memory controller is often used to coordinate the transfer of data to and from a memory device. Each memory access device is coupled to the memory controller through a system bus. The memory controller is in turn coupled to the memory device through a memory bus. Access to the system bus and thus to the memory controller is typically coordinated by a system bus arbiter. From the memory access device's point of view, the memory device is just a data warehouse. The memory access device does not need to know how the data is stored in memory.
In a typical memory, successive data units or “words” are stored in successive columns in memory. The order in which these words are acccessed depends on the endianess of the memory device. A “little endian” memory device stores the least significant word part of a double word group into the smaller address location of a double word location in the memory, and stores the most significant word part of the double word group in the larger address location of the double word location. In contrast, a “big endian” memory device stores the least significant word part of a double word group in the larger address location of a double word location and stores the most significant word part of the double word group in the smaller address location of the double word location.
In some applications, it may be desirable to have multiple devices having different endianess access the same memory space. A “little endian” memory access device views the smaller and larger double word locations, in terms of their addresses, as containing the least significant word part and the most significant word part, respectively, of a double word group. In contrast, a “big endian” memory access device views the smaller and larger double word locations as containing the most significant word part and the least significant word part, respectively, of a double word group.
In a system having multiple memory access devices, which can have different endianess, data words stored in a memory location by one device could be retrieved by another device with a different endianess. If the system bus is wider than the memory bus, a memory access device with a different endianess would view the data words on the system bus differently than the other memory access device. As a result, the data words retrieved from shared memory could be put on the wrong portion of the system data bus if the endianess of each memory access device is not taken into careful consideration. To avoid this difficulty, multi-processor systems typically require all devices sharing the same memory space to have the same endianess. Alternatively, the memory could be split into “bit endian” and “little endian” areas such that devices having different endianess would not share the same memory space.
This type of arrangement, with the system bus being wider than the memory bus, is common for systems containing a double data rate (DDR) synchronous dynamic random access memory (SDRAM). A DDR SDRAM transfers data on each rising and falling edge of a memory clock signal. A DDR SDRAM therefore transfers two data units per clock cycle. For example, a x16 DDR SDRAM has a 16-bit memory data bus which transfers one 16 bit half word on each clock edge. Therefore one 32-bit word is transferred during each memory clock cycle. A x32 DDR SDRAM has a 32-bit memory data bus, with one 32-bit word being transferred on each clock edge for a total of one 64-bit double word transfer for each memory clock cycle. A typical system bus has 64 data bits. Thus when a x16 DDR SDRAM is used, the width of the system bus (64 bits) is wider than the effective width of the memory bus (32 bits).
An improved memory interface is therefore desired which is capable of maintaining consistent data storing and retrieving in a shared memory space by more than one memory accessing device having different endianess, particularly for use with a DDR SDRAM.
SUMMARY OF THE INVENTION
One embodiment of the present invention relates to a method for addressing a memory device. The method includes the steps of: receiving a system address from a memory access device having an endianess, wherein the system address has a word address bit corresponding to word boundaries within the memory device; selectively inverting the word address bit as a function of the endianess of the memory access device to produce a selectively modified system address; and accessing a memory location with the memory device based on the selectively modified system address.
Another embodiment of the present invention relates to a memory interface. The memory interface includes a write data path and a read data path extending through the memory interface, a system address input and a memory address output. The system address input has multiple bits, including a word address bit. A memory address generator is coupled between the system address input and the memory address output. An endianess flag within the memory interface indicates an endianess of a memory access device coupled to the system address input. A selective inversion circuit is coupled in series between the word address bit of the system address input and the memory address generator and includes an inversion control input coupled to the endianess flag.
Yet another embodiment of the present invention relates to a computer system, which includes a memory bus, a system bus, a memory device coupled to the memory bus and a memory access device coupled to the system bus. The memory access device has an endianess and generates a system address on the system bus, which has a word address bit corresponding to word boundaries within the memory device. A memory interface device is coupled between the system bus and the memory bus and includes a selective inversion circuit for selectively inverting the word address bit as a function of the endianess of the memory access device to produce a selectively modified system address, and includes an address generator for producing a memory address on the memory bus based on the selectively modified system address.
REFERENCES:
patent: 5079742 (1992-01-01), Simpson
patent: 5448521 (1995-09-01), Curry et al.
LSI Logic Corporation
Phan Trong
Westman Champlin & Kelly
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