Electronic system with self-test function and simulation...

Details Electronic system with self-test function and simulation... Electronic system with self-test function and simulation...

1999-07-08

2002-06-04

Decady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000

Reexamination Certificate

active

06401226

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic system with a self-test function capable of evaluating operation results of a tested circuit, and a simulation system of the electronic system capable of simulating the operation of the electronic system.
2. Description of Related Art
FIG. 23
is a block diagram showing a configuration of a conventional electronic system with a self-test function. In
FIG. 23
, the reference numeral
1
designates a pseudo-random test pattern generator for serially outputting data constituting a pseudo-random test pattern;
2
designates a scan-path circuit that acquires a pseudo-random test pattern by loading the data serially output from the pseudo-random test pattern generator
1
, and supplies a logic circuit to be tested (simply called “tested circuit” from now on)
3
with the pseudo-random test pattern in parallel, and that loads an operation result of the tested circuit
3
in parallel, and serially outputs data constituting the operation result;
3
designates the tested circuit that receives from the scan-path circuit
2
the pseudo-random test pattern in parallel, executes predetermined logical operations based on the pseudo-random test pattern, and supplies the scan-path circuit
2
with the operation result in parallel;
4
designates a signature register that loads the data serially output from the scan-path circuit
2
, and compresses the operation result; and
5
designates a controller for controlling the pseudo-random test pattern generator
1
, scan-path circuit
2
and signature register
4
.
FIG. 24
is a block diagram showing a configuration of the pseudo-random test pattern generator
1
. In
FIG. 24
, the symbol XOR designates an exclusive-OR circuit; and G
0
-G
4
each designate a flip-flop with a hold function, which holds its data when HOLDG=1, and shifts the data when HOLDG=0. Here, the pseudo-random test pattern generator
1
of
FIG. 24
is an LFSR (Linear Feedback Shift Register) type circuit.
FIG. 25
is a block diagram showing a configuration of the scan-path circuit
2
. In
FIG. 25
, symbols SFF
0
-SFFn−1 each designate a scan flip-flop which carries out a serial shift operation when SM=1, and a parallel input operation from the D terminal when SM=0. Here, the scan flip-flops SFF
0
-SFFn−1 consists of a selector and a flip-flop.
FIG. 26
is a block diagram showing a configuration of the signature register
4
. In
FIG. 26
, the symbol XORF and XOR
3
each designate an exclusive-OR circuit; and SO-S
3
each designate a flip-flop with a hold function, which holds its data when HOLDS=1, and shifts the data when HOLDS=0. Here, the signature register
4
of
FIG. 26
is an FSR (Feedback Shift Register) type circuit.
Next, the operation of the conventional electronic system with a self-test function will be described.
The electronic system with a self-test function executes the evaluation of the operation of the tested circuit
3
through the following roughly divided four processings.
(1) Set initial patterns to the pseudo-random test pattern generator
1
, scan-path circuit
2
and signature register
4
.
To prevent undefined operation of the electronic system, a processing is carried out first for setting initial values to the flip-flops G
0
-G
4
in the pseudo-random test pattern generator
1
, to the scan flip-flops SFF
0
-SFFn−1 in the scan-path circuit
2
, and to the flip-flops S
0
-S
3
in the signature register
4
. The setting of the initial values are carried out by the controller
5
or by an initializing circuit not shown.
(2) Supply the pseudo-random test pattern from the scan-path circuit
2
to the tested circuit
3
in parallel, and feed the operation result back from the tested circuit
3
to the scan-path circuit
2
in parallel (the initial pattern, which is supplied as the pseudo-random test pattern at the first time, may be other than a pseudo-random test pattern).
Holding the pseudo-random test pattern, the scan-path circuit
2
supplies the tested circuit
3
with values held by the scan flip-flops SFF
0
-SFFn−1 from their Q terminals.
Thus, the tested circuit
3
receives from the scan-path circuit
2
the pseudo-random test pattern in parallel, executes the logical operation in accordance with the pseudo-random test pattern, and supplies the operation result to the scan-path circuit
2
in parallel.
Since the controller
5
places SM at “0” in this case, the scan-path circuit
2
captures in parallel through the D terminals the operation result output from the tested circuit
3
, and stores the data constituting the operation result into the scan flip-flops SFF
0
-SFFn−1.
At this stage, since the controller
5
places the HOLDG and HOLDS at “1”, the pseudo-random test pattern generator
1
and scan-path circuit
2
hold the data rather than shift the data.
(3) Execute n-time shift operation of the pseudo-random test pattern generator
1
, scan-path circuit
2
and signature register
4
(where n is the number of stages of the scan-path circuit
2
).
The pseudo-random test pattern generator
1
serially supplies from the SOG terminal to the scan-path circuit
2
the data constituting the pseudo-random test pattern. More specifically, when the controller
5
places the terminal HOLDG at “0” after the initial set of the flip-flops G
0
-G
4
in the pseudo-random test pattern generator
1
, the pseudo-random test pattern generator
1
starts receiving a clock signal, and shifts its data in synchronism with the clock signal. For example, when the initial values “11111” are set to the flip-flops G
0
-G
4
, (see, STATE
0
of FIG.
27
), the values stored in the flip-flops G
0
-G
4
vary as shown in
FIG. 27
every time the clock pulse is supplied, and the value stored in the flip-flop GO is serially supplied to the scan-path circuit
2
.
Since the controller
5
sets SM of the scan-path circuit
2
at “1” in this state, the scan-path circuit
2
serially loads through the SI terminal the data constituting the pseudo-random test pattern serially output from the pseudo-random test pattern generator
1
(the value stored in the flip-flop G
0
) in response to the clock signal, and stores the data into the scan flip-flop SFFn−1. At the same time, the scan flip-flops SFF
0
-SFFn−1 each shift their data to their right neighboring scan flip-flops. Thus, the data held by the scan flip-slop SFF
0
is serially supplied to the signature register
4
every time the clock pulse is supplied.
The shift operation, which is carried out by the number of stages of the scan-path circuit
2
, is completed when the data previously loaded into the scan flip-flop SFFn−1 by the parallel input of the operation result from the tested circuit
3
(the foregoing processing (2)) is transferred to the signature register
4
.
At the same time that the shift operation is completed, the tested circuit
3
completes the output of the operation result, and the scan flip-flops SFF
0
-SFFn−1 complete the storing of the data constituting the pseudo-random test pattern.
Because the controller
5
sets the signal HOLDS at “0” in this state, the signature register
4
, receiving the clock signal, serially loads through the SIS terminal the data constituting the operation result of the tested circuit
3
, which is output from the scan flip-flop SFF
0
of the scan-path-circuit
2
. Receiving the data constituting the operation result, the signature register
4
compresses the data by carrying out the shift operation in synchronism with the clock signal, thereby compressing the n-bit operation result into 4-bit data. Thus, the values stored in the flip-flops S
0
-S
3
become the operation result when the shift operation has been iterated n times.
(4) Repeat the foregoing processings (2) and (3) (m−1) times.
The scan-path circuit
2
sequentially supplies the tested circuit
3
with (m−1) pseudo-random test patterns following the initial pattern in parallel, and acquires the operation

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