Line buffer type semiconductor memory device capable of...

Details Line buffer type semiconductor memory device capable of... Line buffer type semiconductor memory device capable of...

2000-06-22

2002-02-12

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S230080

Reexamination Certificate

active

06347055

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a line buffer type semiconductor memory device.
2. Description of the Related Art
Recently, in order to enhance the access speed, line buffers for temporarily storing data are introduced into a conventional semiconductor memory device. This line buffer type semiconductor memory device is also called a virtual channel memory where line buffers correspond to channels (see : NEC Corporation, “64M-bit Virtual Channel SDRAM with Double Data Rate”, Preliminary Data Sheet, 1998).
In a prior art line buffer type semiconductor memory device (see the above-mentioned document), a background operation is carried out between a memory section and a line buffer section, and a foreground operation is carried out between the line buffer section and the data buffer. The background operation is constructed by a page open operation, a prefetch operation, a restore operation and a page close operation.
On the other hand, the foreground operation is constructed by a line buffer read operation and a line buffer write operation. This will be explained later in detail.
If the line buffer type semiconductor memory device is accessed by a plurality of memory masters, since the memory addresses of the memory masters have no relationship to each other, or the memory masters have independent localization of memory addresses, page open operations often occur in the line buffer type semiconductor memory device, which may delay the memory access. This is called a memory access mutual interference or a memory access mutual contamination.
In order to avoid the memory access mutual interference, a memory controller is provided to allocate the line buffers of the line buffer section to the memory masters in advance, so that the localization's of memory addresses of the memory masters does not overlap.
In the above-described line buffer type semiconductor memory device, however, since there are four kinds of memory access modes, i.e., a page hit mode, a page mishit mode, a line buffer hit mode a line buffer mishit mode, which have different access times, the management for scheduling the memory access is complex.
Also, even in a page mishit mode or a line buffer mishit mode, at least one page open operation and at least one prefetch operation are carried out to access the line buffer section, which delays the memory access. Additionally, in a line buffer mishit mode, the memory management of what page is opened and the line buffer management of which segments are located in the line buffers are required, which complicates the management of the device.
Particularly, in a prefetch operation where no pages are hot and no line buffers are hit, when one segment is required to be restored and the page including this segment is closed, a long complex sequence is required before the prefetch operation.
Further, when random memory accesses inviting line buffer mishit modes are carried out, background operations are often carried out, which also delays the memory access.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a line buffer type semiconductor memory device capable of simplifying the background operation and reducing the delay of the memory access.
According to the present invention, in a line buffer type semiconductor memory device constructed by a memory section and a line buffer section including a plurality of line buffers each capable of storing data of one segment size, a direct fetch control section reads first data of one segment size from the memory section and writes the first data into one of the line buffers, and a direct restore control section reads second data of one segment size from one of the line buffers and writes the second data into the memory section.


REFERENCES:
patent: 5469381 (1995-11-01), Yamazaki
patent: 10-326225 (1998-12-01), None
NEC Corporation, “64M-BIT Virtual Channel SDRAM with Double Data Rate”, Preliminary Data Sheet, 1998, pp. 1-111.

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