Optics: measuring and testing – By configuration comparison – With comparison to master – desired shape – or reference voltage
Reexamination Certificate
1999-11-29
2002-11-05
Stafira, Michael P. (Department: 2877)
Optics: measuring and testing
By configuration comparison
With comparison to master, desired shape, or reference voltage
Reexamination Certificate
active
06476913
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to inspection method, apparatus, and system for a fine circuit pattern of a semiconductor device, a photomask, a reticle, a liquid crystal, or the like.
An inspection of a semiconductor wafer will now be described as an example.
A semiconductor device is formed by repeating a step of transferring a circuit pattern formed on a photomask to a semiconductor wafer by a lithographing process and an etching process. A state of the process, the presence or absence of generation of a foreign matter (particles), and the like in the manufacturing step of the semiconductor device largely exercise an influence on a manufacturing yield of the semiconductor device. To detect them early or preparatorily, a method of inspecting the circuit pattern of the semiconductor wafer in the manufacturing step of the semiconductor device has conventionally been used.
As an apparatus for inspecting a defect existing in the circuit pattern of the semiconductor wafer, a defect inspection apparatus of a wafer with a pattern such that white light is irradiated to a semiconductor wafer and a plurality of circuit patterns of the same kind are compared by using an optical image has been put into practical use. The outline of the inspection method has been disclosed in “Monthly Semiconductor World”, Vol. August issue, pp. 96-99, 1995. According to the inspection method using the optical image, as disclosed in JP-A-3-167456, there has been disclosed a system such that an optically irradiated region on a wafer substrate is formed as an image by a time delay integrating sensor and characteristics of the image are compared with design characteristics which have previously been inputted, thereby detecting a defect. On the other hand, since the detection of a defect by the optical image is becoming difficult in association with the reduction in size of a circuit pattern, complication of a shape, and variation of material, a method of inspecting a circuit pattern by using an electron beam image whose resolution is higher than that of the optical image has been proposed.
A scanning electron microscopy (hereinafter, abbreviated to SEM) has been known as an apparatus for irradiating an electron beam to a sample and observing it. To obtain a practical inspection time in case of inspecting a circuit pattern formed on a semiconductor wafer by an electron beam image, it is necessary to obtain an image at a speed that is much higher than that of the SEM. It is also necessary to simultaneously assure a resolution of the image obtained at a high speed and an S/N ratio of the image.
As an inspection apparatus for a circuit pattern using an electron beam, a method whereby an electron beam having an electron beam current that is 100 or more times (10 nA or more) as large as that of the ordinary SEM is irradiated to an electrically conductive substrate such as an X-ray mask or the like, any of secondary electrons, reflected electrons, and transmitted electrons which are generated are detected, and images formed from resultant signals are compared and inspected, thereby automatically detecting a defect has been disclosed in “Journal of Vacuum Science Technology B” (J. Vac. Sci. Tech. B), Vol. 9, No. 6, pp. 3005-3009, (1991), “J. Vac. Sci. Tech. B”, Vol. 10, No. 6, pp. 2804-2808, (1992), JP-A-5-258703, and U.S. Pat. No. 5,502,306. According to such a method, the inspection of a fine circuit pattern is executed by the automatic wafer appearance inspection of an electron beam scanning system whose defect detecting performance is superior to that of the optical appearance inspection, and various kinds of defects occurring in a circuit pattern forming step can be detected.
In the above defect inspection, although the images of the adjacent similar circuit patterns are formed and compared to thereby automatically detect a defect, in the inspection, it is necessary to cope with wafers of various pattern layouts or patterns of various materials. To accurately compare the adjacent patterns, it is necessary to previously obtain a layout of the pattern, namely, a layout of a chip (or die) or shot on the wafer and register it as an inspecting condition of the wafer to be inspected (hereinafter, referred to as an inspection-subject wafer). To form an image suitable for inspection in various materials, it is necessary to set brightness of the image and a contrast of the pattern or a background to proper values and register them as inspecting conditions of the inspection-subject wafer. In the above conventional apparatus, however, there is no disclosure about a procedure for setting the inspecting conditions and an operating method, and it takes one to several hours to fully set the proper inspecting conditions with respect to a wafer whose operation is complicated and which newly becomes a target of inspection. In a semiconductor manufacturing line, since a pattern inspection is executed with regard to a plurality of products (namely, a plurality of circuit pattern layouts) and a plurality of steps (namely, a plurality of materials and a plurality of detailed circuit pattern shapes), it is necessary to set a large number of inspecting conditions, so that there is a problem that it takes an extremely long time for various operations in the inspection, particularly, for the inspecting condition setting operations.
To solve the above problem, as a technique such that a data process and parameter setting can be executed in parallel simultaneously with the inspecting operation, a method of transmitting and receiving signals between an operating portion and a mechanism portion for setting data processing parameters simultaneously with the inspection and a mechanism portion has been disclosed in JP-A-63-32604. According to such a method, however, although there is a disclosure about the signal transmission and reception, there is not a disclosure regarding the operability and a data structure for parameters with respect to a complicated inspection apparatus in which the number of input parameters is large.
In various inspections of the system for obtaining an image of a circuit pattern of a substrate and comparing it with an adjacent similar pattern, it is necessary that a layout of the circuit pattern formed on the wafer substrate, namely, a layout of a shot, a layout of a chip (or die) in it, and further, a layout of memory cells, peripheral circuits, logic circuits, test patterns, or the like in it are preliminarily set as inspecting conditions. It is, further, necessary to set conditions of the irradiation light, detecting conditions, image comparing conditions, defect discriminating conditions, and the like in accordance with a detailed shape and a material of the pattern of an inspection-subject wafer. Each time processing conditions of a semiconductor device are changed, it is also necessary to properly change those conditions.
There are the following problems in such a case. For example, when many parameters are sequentially inputted and set, although an operating picture plane is sequentially switched in accordance with the input, the operator cannot know the switching order and items which are switched. Therefore, even with respect to the items which do not need to be inputted, the picture plane is shifted to the next picture plane after they are once displayed on the picture plane and confirmed, so that an efficiency is low.
There are also problems such that when the data which has already been inputted is confirmed again or inputted, the present picture plane cannot be returned to the previous picture plane or, since the present input stage is obscure, the layer of the picture plane to be returned is unknown, so that the present picture plane cannot be returned to the previous picture plane unless many operations are performed, and the like.
In still another conventional apparatus, although a plurality of parameter input picture planes can be displayed on a workstation for operation by a window format, since a plurality of windows are overlapped and displayed even in such a system, the operat
Hiroi Takashi
Ito Maki
Machida Kazuhisa
Morioka Hiroshi
Nozoe Mari
Hitachi , Ltd.
Kenyon & Kenyon
Stafira Michael P.
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