Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-28
2002-08-20
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C341S120000
Reexamination Certificate
active
06438721
ABSTRACT:
FIELD OF INVENTION
The invention relates generally to the field of electronic circuits and more particularly to the testing of clock positioning circuits.
BACKGROUND OF INVENTION
FIG. 1
is a prior art block drawing illustrating a general system
10
designed to align two clock signals. Such a system may be used, for example in memory subsystems for PCs and other computer based systems. [As will be explained below, the particularly relevant blocks to the invention, namely the phase select logic
20
(digital in nature) and the interpolator
16
(analog in nature), can also be used in systems that need to align a clock to a serial data stream. Such systems have usefulness in many types applications, such as gigabit ethernet, computer backplanes, and telecommunications systems.]
In
FIG. 1
, a phase locked loop
14
generates eight free running clock signals evenly spaced in phase. From these eight phase signals, a clock signal is generated that when divided down becomes the PCLK input of a phase detector
12
and is phase aligned to the SYNCLK input. In the example system
10
, the output of an interpolator block
16
b
has a frequency of 400 MHz, which is divided down to 25 MHz at the input of the phase detector
12
. (Interpolator
16
is illustrated as
2
blocks in FIG.
1
: a current switch array
16
a
and interpolator
16
b
). Two multiplexors
18
a
and
18
b
each take four of the clock signals generated by the phase lock loop
14
and pass one of them to interpolator
16
b
based on a selection signal from the sector register in the phase select logic
20
. A current switch array
16
a
also receives a sixteen-bit control word from phase select logic
20
. The interpolator
16
generates a clock signal somewhere in between the two clock phases it receives from multiplexors
18
a
and
18
b.
When all sixteen bits of a control word are logic 0, the output of the interpolator will be in phase with the clock phase from multiplexor
18
a.
When all sixteen bits of a control word are logic 1, the output of the interpolator will be in phase with the clock signal from multiplexor
18
b.
All other control words result in a clock that is positioned somewhere between these two extremes. The output of the interpolator is divided down by divider
22
to generate the PCLK input to phase detector
12
. The phase detector
12
analyzes the phase difference between the SYNCLK and PCLK inputs and decides whether the phase of PCLK should be advanced or retarded. This decision is sent to the phase select logic
20
via the DIR signal. The interpolator
16
is physically located in an analog circuitry portion of system
10
.
FIG. 2
is prior art drawing illustrating the interpolator
16
in further detail. The current switch array
16
a consists of sixteen current source transistors T
1
-T
16
connected to sixteen differential transistor pairs D
1
-D
16
. The sixteen current source transistors all have the same channel width and thus are the same size to output identical units of current Iu. The differential pair outputs are connected to node SRCO and node SRCE of an interpolator block
16
b.
The sixteen differential transistor pairs are controlled by sixteen D flip-flops FF
1
-FF
16
that form a thermometer code register
20
a.
The thermometer code register
20
a
is referred to as such because the bits B
0
-B
16
are always a sequence of logic 0's followed by a sequence of logic 1's during normal operation. The flip flops and the differential pairs determine whether the currents from the current source transistors go through node SRCE or node SRCO. When the output of a flip flop is logic 1, that unit current is steered through SRCO and when the output is logic 0, the current is steered through node SRCE. Thus if n of the bits are logic 1, current IO will be n Iu and current IE will be (16−n)Iu.
The interpolator block
16
b
receives the two clock phases from multiplexors
18
a
and
18
b.
A first differential transistor pair P
1
receives the clock phase from multiplexor
18
a
on transistors IN
1
P and IN
1
N and a second differential transistor pair P
2
receives the clock phase from multiplexor
18
b
on transistors IN
2
P and IN
2
N. Interpolator
16
is referred to as a current mode interpolator because the phase of the output clock is determined by the ratio of IO to the sum of IO and IE.
Recall that the application of the system of prior art
FIG. 1
is to minimize the phase difference between the PCLK and SYNCLK inputs and ideally force this phase difference to zero. In the application wherein the system
10
is employed in a computer memory system operating at about 400 MHz, a single missing code in the current switch array
16
a
may result in an increase of the phase difference of only around 10 picoseconds; that is, the clock phase can be positioned to about 10 picosecond resolution. The missing code in the current switch array
16
a
could result from a variety of different sources, such as, for example, a stuck phase select code register bit from phase select block
20
of
FIG. 1
or a bad differential pair D
1
-D
16
within current switch array
16
a.
The 10 picosecond resolution is not a catastrophic failure and the device employing the system will pass typical external tests that are applied to the pins of the device (the system
10
is typically part of an integrated circuit having input/output package pins); however, the device is not optimal and the manufacturer probably would not want to ship it to a customer. The problem with the typical external tests is that the manufacturer cannot identify if an individual one of the current sources is bad from the pin boundary of the device. Thus, manufacturing defects of the clock positioning circuit are unable to be located by looking at the outputs of a tester.
Some prior art test techniques employ scan boundary methods to perform internal test. Such methods are unsuitable for the device of prior art
FIGS. 1 and 2
as the clock positioning circuit is very timing sensitive. What is needed is a method to test for defects within the current switch array and phase select block without impacting the normal timing of the device.
It is accordingly an object of the invention herein to provide a method for testing a current mode interpolator.
Other objects and advantages of the invention herein will be apparent to those of ordinary skill in the art having the benefit of the description herein.
SUMMARY OF THE INVENTION
A built in self test method checks a current mode clock interpolator circuit by controlling the state of a thermometer code register and comparing the current from a current switch array to a reference current.
REFERENCES:
patent: 5748125 (1998-05-01), Goderbaum et al.
patent: 5786778 (1998-07-01), Adams et al.
patent: 5955980 (1999-09-01), Hanna
patent: 6005425 (1999-12-01), Cho
Brady III W. James
Hernandez Pedro P.
Moise Emmanuel L.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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