Semiconductor memory device and method of repairing same

Details Semiconductor memory device and method of repairing same Semiconductor memory device and method of repairing same

2001-07-18

2002-08-20

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S191000

Reexamination Certificate

active

06438047

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device and a method of repairing the same.
2. Description of Related Art
In general, a memory cell array of a semiconductor memory device comprises a normal memory cell array and a redundant memory cell array. When defective normal cells are detected at wafer level during production, the defective normal memory cells may be deactivated and the redundant memory cells brought online, thereby reducing the number of rejects in the manufacturing process. However, even though the semiconductor memory device is thus repaired by being replaced with the redundant memory cells at wafer level, when the semiconductor memory device is tested at a package level, defective memory cells may still be found.
More than about 80% of memory defects at the packaging level are attributable to failure of 1-bit or 2-bit memory cells. Thus, if a defective 1-bit or 2-bit memory cell can be repaired, the yield of semiconductor memory devices can be significantly improved.
Typically, in order to repair a semiconductor memory device at a package level, redundant cells are arranged between adjacent data I/O line pairs that configure data I/O line groups located between memory cell array blocks, so that the redundant cells may be brought online. However, as a capacity of the memory cell array increases, an intervals between the memory cell array blocks becomes narrower and it becomes increasingly difficult to arrange redundant cells between data I/O line pairs.
SUMMARY OF THE INVENTION
Preferred embodiments of the invention provide a semiconductor memory device, comprising a memory cell array receiving and outputting data through data I/O line groups; at least one redundant cell control for storing a defective cell address, generating a redundant cell enable control signal when the defective cell address is equal to an input cell address, generating a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generating a redundant cell write control signal during a write operation in response to the redundant cell enable control signal; a sense amplifier connected to an I/O line group commonly connected to the data I/O line groups, amplifying and outputting data outputted from the memory cell array during the read operation, and disabled in response to the redundant cell read control signal; and at least one redundant cell means storing input data transferred to the I/O line group in response to the redundant cell write control signal and outputting stored data in response to the redundant cell read control signal.
Preferably, the sense amplifier comprises a current amplifier to detect and amplify a current difference of respective I/O line pairs of the I/O line group and a driver to drive the output signals of the current amplifying means.
A preferred embodiment of the invention further provides a semiconductor memory device, comprising a memory cell array receiving and outputting data through data I/O line groups; at least one redundant cell control storing a defective cell address, generating a redundant cell enable control signal when the defective cell address is equal to an input cell address, generating a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generating a redundant cell write control signal during a write operation in response to the redundant cell enable control signal; a sense amplifier amplifying data transferred through the data I/O line groups and transferring the data to an I/O line group commonly connected to the data I/O line groups during the read operation, and disabled in response to the redundant cell read control signal; and at least one redundant cell storing input data transferred to the I/O line group in response to the redundant cell write control signal and outputting stored data in response to the redundant cell read control signal.
The sense amplifier detecting and amplifying a voltage difference of data transferred through the data I/O line groups.
Another preferred embodiment of the invention provides a method of repairing a semiconductor memory device comprising a memory. cell array for receiving and outputting data through data I/O line groups and an I/O line group commonly connected to the data I/O line groups. The method comprises storing a defective cell address in response to all control signals; generating a redundant cell enable control signal when an input address is equal to the defective cell address; generating a redundant cell read control signal during a read operation and generating a redundant cell write control signal during a write operation in response to the redundant cell enable control signal; and outputting data stored in a redundant cell in response to the redundant cell read control signal during the read operation, and storing input data from the redundant cell in response to the redundant cell write control signal during the write operation.


REFERENCES:
patent: 5696724 (1997-12-01), Koh et al.
patent: 6292413 (2001-09-01), Kato et al.
patent: 404134787 (1992-05-01), None
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndpp. 169-170.

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