Shrink-wrap collar for DRAM deep trenches

Details Shrink-wrap collar for DRAM deep trenches Shrink-wrap collar for DRAM deep trenches

1995-06-06

2002-06-04

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S059000, C257S072000, C257S303000, C257S306000, C257S310000, C257S311000, C257S410000, C257S443000

Reexamination Certificate

active

06399976

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the formation of trench structures in semiconductor electronic devices and, more particularly, to the formation of deep trench capacitor structures for integrated circuit memories.
2. Description of the Prior Art
The need for memory structures of increased device density has generally followed similar trends in other integrated circuit devices such as microprocessors in order to provide improvements in speed and function as well as economies of manufacture, so long as manufacturing yields can be maintained. Decreased circuit element size is generally accompanied by decreases in parasitic capacitances and decreased signal propagation time between circuit elements. The increase in number of circuit elements which can be formed on a single chip yields increases in functionality. Likewise, an increase in the number of circuit elements which can be formed on a single chip or wafer yields economies in manufacturing processes since more devices and chips can be simultaneously formed. However, in any given technology and for any particular design ground rules, such as minimum feature size, there is a trade-off between the minimum size or maximum integration density which can be achieved and the manufacturing yield.
Devices which rely on particular dimensions for their electrical properties, such as capacitors used in dynamic memories (e.g. dynamic random access memories (DRAM's)), however, present additional trade-offs in design. For example, if the area of capacitor plate electrodes is reduced (for a given electrode spacing and dielectric constant of the material therebetween) the capacitor value and charge storage capacity at a given working voltage will be reduced. (Of course, capacitance may be increased by reduction of electrode spacing, consistent with capacitor size reduction in integrated circuits, but reduction in charge storage can seldom be fully compensated as capacitor size is reduced.) On the other hand, if the capacitance of each cell is reduced to increase the number of cells without corresponding decrease in parasitic capacitance of word and bit lines connected to the memory cells, operating margins may be severely compromised. Further, as charge storage is reduced, other effects such as charge leakage become more critical to reliable operation. In view of these conflicting design considerations, so-called deep trench capacitor structures have become well-developed for the purpose of reducing capacitor “footprint” size on the chip or wafer while maintaining satisfactory capacitance values. However, deep trench (or, simply, “trench”) capacitors are still subject to charge leakage.
Charge leakage, in particular, is of particular concern since capacitance of individual memory cell capacitors is necessarily small. At current levels of DRAM capacitor technology, a stored data bit may be represented by only several hundred electrons or even fewer. Therefore, even slight charge leakage may be sufficient to cause loss or at least compromise of stored data unless the memory refresh period is reduced. Corresponding increase in memory refresh frequency effectively increases average memory access time since the memory cannot be accessed during refresh operations.
Charge leakage is principally attributed to crystal lattice dislocations in the vicinity of the boundary of the capacitor. Such crystal lattice dislocations are believed to be due to stresses which may be caused during capacitor fabrication which are later relieved by the formation of crystal lattice dislocations. Thus, crystal lattice dislocations may form wherever such stresses are present and extend over a distance greater than the transverse dimension of the capacitor, itself. For example, present lithographic capabilities for trench capacitor technology allow a 0.25 &mgr;m capacitor size to be approached while crystal lattice dislocations can often extend 0.5 &mgr;m or more from the capacitor boundary. Therefore, full exploitation of potential integration density at the current state of lithographic technology is limited by permissible proximity of trench capacitors which cannot be spaced closer than twice the likely extent of crystal lattice dislocations without comprising isolation between capacitors.
Additionally, as trench dimensions of 0.25 &mgr;m are approached, it has been observed that crystal lattice dislocation density increases dramatically and has been observed as high as 100% (i.e. at least one dislocation at each capacitor) even at 0.5 &mgr;m dimensions, particularly when the “heat budget” subsequent to trench formation is not or cannot be sufficiently limited. It is theorized that this observed increase in crystal lattice dislocation density at reduced capacitor dimensions may be due, in significant degree, to the greater fraction of the trench which is occupied by the oxide dielectric collar when trench dimensions are decreased. Oxides deposited in recesses in a substrate or layer of semiconductor material can produce compressive stresses in the surrounding material by a variety of mechanisms and the greater proportion of oxide may produce relatively greater stresses and/or strain which cannot be withstood by the relatively smaller amount of surrounding material.
The mechanisms by which compressive stresses can occur are not unique to oxides. Numerous processes common in semiconductor manufacture result in volume expansion of a body of material. If the expanded material is surrounded by another material which does not undergo an equal or greater volume expansion, a compressive force will result. For example, a differential in thermal expansion between a body material and another material surrounding it is a reversible mechanism which can nevertheless cause stresses corresponding to the temperature excursion. Annealing relieves internal stresses, including stresses due to differential thermal expansion, at a high temperature but if differential contraction occurs when the materials are cooled, stresses will again occur and will be persistent. This effect is particularly true of oxides which shrink less than the substrate when cooled, resulting in persistent compressive stresses. Volume change may also occur during annealing due to changes in the crystal structure (e.g. amorphous to polycrystalline) at high temperature compressive stresses can also result from a volume increase in films due to inclusions or growth of materials (e.g. grown oxides), which may not be fully avoidable or occur spontaneously during other processes (e.g. impurity diffusion).
Given that a reduction in “footprint” of trench capacitors and other trench structures necessarily implies formation of structures within a body of material and the general tendency for routine processing to cause volume expansion of the enclosed material, the likelihood of compressive forces resulting in the material surrounding the trench is substantial. While several mechanisms such as recrystallization and chemical reactions are known to cause volume reduction, many are not compatible with devices being fabricated and volume reduction is generally very small and not well-controllable. In any event, at the present state of the art, a solution to the problem of formation of crystal lattice dislocations is necessary to enable further increases in integration density of trench structures in general and deep trench capacitors in particular and to exploit the present capabilities of lithographic processes for integrated circuit manufacture.
Hydrogenated films of various materials are known in the art and a small hydrogen content is recognized to increase growth rates of deposited material and to produce some other generally desirable effects on the film. It is theorized that hydrogen fills dangling bonds in as-deposited amorphous material and may thus accelerate deposition or film growth. However, it is generally considered desirable to limit the amount of hydrogen in the film and to maintain the beneficial effects of hydrogenation by maintaining the hydro

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