Single bit Sigma Delta filter with input gain

Details Single bit Sigma Delta filter with input gain Single bit Sigma Delta filter with input gain

1999-10-27

2002-06-18

Chin, Stephen (Department: 2634)

Pulse or digital communications

Pulse code modulation

Differential

C375S350000, C341S143000, C341S144000, C341S155000, C708S307000

Reexamination Certificate

active

06408031

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to digital filtering of a single bit data stream input. Particularly, it relates to an architecture for an improved digital filter that requires less complex computations.
BACKGROUND OF THE INVENTION
Digital filters, such as Infinite Impulse Response (hereinafter “IIR”) filters, have been implemented with Delta Modulator architectures. Delta modulation can be described as a type of Pulse Code Modulation where only 1-bit encoding is used. One-bit encoding is made possible by a feedback loop which is an integral part of the encoding process.
FIG. 3
illustrates exemplary components of a Delta modulation system applicable to a single message. The overall action of the Delta modulator is to transmit 1-bit information about the changes in f(t) over time.
It is also known in the art that systems using delta modulation are not well suited to messages having DC components and to messages having an approximately flat power spectrum. Delta modulation performs most favorably when the message has no DC component and when the power density spectrum decreases with increasing frequency. A modified delta modulation system, called Delta Sigma Modulation, exits that performs better with DC components and flat power spectrum density. Delta Sigma Modulation (also called Sigma Delta Modulation) is formed by adding one integrator and one differentiator to a basic Delta Modulation system.
FIG. 4
shows a known Sigma Delta architecture for implementing a first order IIR filter. The first order filter sections can be implemented with the denominator coefficient multiplying the single bit output in a feedback configuration and the numerator coefficient multiplying the single bit input in a feedforward configuration. In particular,
FIG. 4
illustrates a summing node
50
that receives and sums together inputs from the input signal
52
, a delayed feedforward term from a module
54
, and a feedback term output from a sigma delta modulator
56
.
The numerator or feedforward term of
FIG. 4
consists of a register containing the value of the zero a
0
. The feedforward term is added at the input summing node using a simple adder. The feedback term consists of a register containing the value of the pole b
0
. As with the feedforward term, this multiplication is performed by simply adding or subtracting register values which contain the partial feedback coefficients (1−b
0
).
Often, in addition to implementing the filter transfer function, applications exist where it is desirable to add gain or attenuation into the system. In the case where the zero is chosen to lie on the unit circle, the single input then takes the form of an addition or subtraction. However, for the more generalized case where the numerator coefficient is not equal to 1 (i.e. not on the unit circle) the ability to add gain into the system requires a (multibit)×(multibit) multiplication due to the gain factor being multiplied by the non-unity numerator coefficient. (Multibit)×(multibit) multiplication is more complicated and computationally more expensive that single bit multiplication. Single bit multiplication can be implemented with simple adders and/or subtractors, while multibit×multibit multiplication requires a hardware multiplier.
Accordingly, there is a need to implement a digital filter having a gain or attenuation value that does not require a (multibit)×(multibit) multiplication.
SUMMARY OF THE INVENTION
Computationally expensive multiplication can be reduced in a digital circuit for filtering an input signal, according to the invention, with a digital circuit having a first gain stage, a delay element, a feed-forward stage, and a summer. The first gain stage generates a gain corrected signal by multiplying the input by a gain G. The delay element forms a delayed gain corrected signal by delaying the gain corrected signal for one cycle. The feed-forward stage generates a feed-forward signal by delaying and multiplying the input signal by a gain B. The summer then generates an output signal by summing together the gain corrected signal, the delayed gain corrected signal, and the feed-forward signal. The architecture of the digital circuit allows for digital filtering of the input signal without computationally expensive multibit×multibit multiplications.
Another aspect of the invention provides for a method of filtering an input signal. The method includes generating a gain corrected signal; forming a delayed gain corrected signal; generating a feed-forward signal; and summing together the gain corrected signal, the delayed gain corrected signal and the feed-forward signal to generate an output signal. The gain corrected signal is generating by multiplying the input signal by a gain G. The delayed gain corrected signal is formed by delaying the gain corrected signal for one cycle. The feed-forward signal is generated by delaying the input signal by one cycle and by multiplying the delayed input signal by a gain B.


REFERENCES:
patent: 5629701 (1997-05-01), Ritoniemi et al.
patent: 5736950 (1998-04-01), Harris et al.
patent: 5757299 (1998-05-01), Noro et al.
patent: 6191715 (2001-02-01), Fowers

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