Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
1999-09-23
2002-11-05
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S502000, C382S162000, C382S276000, C327S141000
Reexamination Certificate
active
06477656
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a clock pulse generating circuit, and in particular, to a clock pulse generating circuit which adjusts the number of pulses of a drive clock pulse within a predetermined time to be a predetermined number.
In an image forming apparatus, an image is formed on an image bearing member by scanning the image bearing member which is rotating in the direction of sub-scanning by a laser beam which is modulated in accordance with image data in the direction of main scanning. In this case, on the basis of a drive clock pulse called a dot clock pulse, the laser beam is modulated by the image data.
Accordingly, in accordance with the predetermined number of pulses of the dot clock pulse, it is necessary to generate the dot clock pulse in order that the length of the image to be formed on the image bearing member in the direction of main scanning may be always constant.
Further, in recent years it has been developed a color image forming apparatus equipped with a plurality of units comprising means for charging, exposure, and development respectively in the neighborhood of the image bearing member forming color toner images on the image bearing member in one rotation of it, and transferring the images altogether onto a sheet of recording paper at a time. On the other hand, it has also been developed a color image forming apparatus equipped with a plurality of image bearing members in the neighborhood of an intermediate transfer member and equipped with means for charging, exposure, development, and transfer around the image bearing members respectively, transferring the toner images having been formed on the respective image bearing members sequentially onto the intermediate transfer member, and transferring the color toner images born on the intermediate transfer member altogether onto a sheet of recording paper at a time.
In an image forming apparatus of the former type, in some cases the length of the image formed on the image bearing member in accordance with the predetermined number of pulses of the dot clock pulse fluctuates owing to the fluctuation of the number of rotation of the polygonal mirror which carries out main scanning and to the aberration of the optical system.
On the other hand, in an image forming apparatus like the latter one which uses a plurality of means for exposure to form color toner images on the image bearing member and on the intermediate transfer member, owing to the dispersion of the characteristics of the optical systems such as the polygonal mirror and a lens in the respective means for exposure, the dispersion of the length of image formed on the image bearing member in the main scanning direction is produced among the respective means for exposure, resulting in producing a color deviation.
In such cases as described in the above, it is desirable that the timing (phase) and the frequency of rising up of dot clock pulses can be adjusted.
For a circuit as mentioned in the above that makes it possible to adjust the phase and the frequency, a VCXO (crystal oscillator of a voltage control type) and a DDS (digital direct synthesizer) have been known.
These VCXO and DDS are of no problem in precision, but they are not suitable to generation of a dot clock pulse in an image forming apparatus for the reasons that they make the cost of the apparatus high and that they are independent devices respectively which are not suitable to make the system of one chip (integration of circuits).
SUMMARY OF THE INVENTION
This invention has been performed in order to solve the above-mentioned problems, and it is an object of the invention to provide a clock pulse generating circuit capable of generating a dot clock pulse whose number of pulses generated in a predetermined time is fixed to a predetermined number in a single integrated circuit without using an additional part.
That is, this invention as means for solving the problems is such one as to be explained in the following:
An image forming apparatus, comprises:
an image forming device to scan in a main scanning direction in synchronization with dot clock pulses for each scanning line so as to form an image;
a basic clock pulse generating section to generate basic lock pulses with a predetermined interval;
a delayed clock pulse generating section to generate a group of plural delayed clock pulses having different phases respectively by delaying the basic clock pulse generate by the basic clock pulse generating section into plural delay stages;
a synchronism detecting section to detect at least two delayed clock pulses synchronizing with an index signal from the plural delayed clock pulses generated by said delayed clock pulse generating section;
a calculating section to calculate a number of delay stages existing within a given time period on the basis of the two synchronizing delayed clock pulses detected by the synchronism detecting section; and
a clock pulse control section to selecting the delayed clock pulses sequentially delayed from the synchronizing delayed clock pulse from the group of plural delayed clock pulses within a predetermined time period on the basis of the calculated number of delay stages so as to control a number of clock pulses outputted as the dot clock pulses during the predetermined time period.
As a result of this, it is possible that the length of the image to be formed in the direction of the main scanning direction may be made always constant.
A clock pulse generating device, comprises:
a basic clock pulse generating section to generate basic lock pulses with a predetermined interval;
a delayed clock pulse generating section to generate a group of plural delayed clock pulses having different phases respectively by delaying the basic clock pulse generate by the basic clock pulse generating section into plural delay stages;
a synchronism detecting section to detect at least two delayed clock pulses synchronizing with an index signal from the plural delayed clock pulses generated by said delayed clock pulse generating section;
a calculating section to calculate a number of delay stages existing within a given time period on the basis of the two synchronizing delayed clock pulses detected by the synchronism detecting section; and
a clock pulse control section to selecting the delayed clock pulses sequentially delayed from the synchronizing delayed clock pulse from the group of plural delayed clock pulses within a predetermined time period on the basis of the calculated number of delay stages so as to control a number of clock pulses outputted during the predetermined time period.
As a result of this, if is adopted to the scanning device, it is possible that the length of the image to be formed in the direction of the main scanning direction may be made always constant.
(1) A clock pulse generating circuit comprising a basic clock pulse generating section for generating closk pulses with a predetermined interval and a delayed clock pulse generating section for generating a group of a plurality of delayed clock pulses having different phases respectively by delaying the basic clock pulse generated by said basic clock pulse generating section, selecting sequentially delayed clock pulses having different phases respectively out of said plurality of delayed clock pulses, and generating clock pulses having a number of pulses generated within a predetermined time made to be a predetermined number by synthesizing these selected clock pulses.
In this clock pulse generating circuit, delayed clock pulses having different phases respectively is selected sequentially out of said plurality of delayed clock pulses, and clock pulses having the number of pulses generated within a predetermined time made to be a predetermined number is generated by synthesizing these selected clock pulses.
That is, the number of pulses within a predetermined time is adjusted not by a fine adjustment of the clock pulse frequency but by sequentially selecting the delayed clock pulses having their phases finely varied without varying the frequency within the predetermined time.
As
Azumai Mitsuo
Izumiya Kenji
Takaki Kouichi
Du Thuan
Frishauf Holtz Goodman & Chick P.C.
Konica Corporation
Lee Thomas
LandOfFree
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