Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-01-06
2002-06-04
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S713000, C438S720000
Reexamination Certificate
active
06399508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method for etching conductive layers in a semiconductor structure. In particular, the present invention pertains to a method for etching conductive layers using an inorganic dielectric hard mask, as opposed to a conventional organic photoresist, in conjunction with a chlorine-based plasma.
2. Brief Description of the Background Art
In modern semiconductor processing, highly integrated circuit chips, such as a chip which is capable of performing the very fast logic operations required by a personal computer's central processing unit (CPU), have feature sizes in the range of about 0.25 &mgr;m or smaller. In the technology of semiconductor device fabrication, lithography (or photolithography) plays an import role in the continuing trend toward smaller device feature sizes. Lithography is a key technology in semiconductor manufacturing, because it is used repeatedly in a process sequence that depends on the device design. Progress in lithography techniques is reflected in more advanced (and smaller) devices.
Basic steps of the lithographic process include spin coating of the photoresist on a substrate, exposure, and development of a photoresist mask. In order to increase the resolution and reliability of a transferred pattern, a number of steps, including dehydration bake, priming, soft bake, and hard bake, are performed on the photoresist mask for the purpose of enhancing its primary function of precise pattern formation and protection of the substrate during etching.
Conventional optical photoresist materials include a resin, a sensitizer, and a solvent. The resin serves as a binder and establishes the mechanical properties of the film; the sensitizer is a photoactive compound; and the solvent serves to maintain the photoresist in a liquid state until it is applied to the substrate being processed. Since the properties of the resultant product are affected by the performance of an optical photoresist, it is very important to take into consideration the optical properties (such as resolution and photosensitivity) and the mechanical properties (such as adhesion, etch resistance, and thermal stability) of the photoresist.
The etching of metal or metal alloy films is a very important step in the fabrication of semiconductor devices, such as integrated circuits. On many of the most advanced devices, the device density is limited by the area occupied by the interconnect paths which form the conductivity of the device. The optical photoresist requires enhanced mechanical properties to withstand etching and implantation, as well as to increase the selectivity of etching the conductive material relative to the photoresist. The selectivity for etching the material to be etched relative to the photoresist typically ranges between about 2:1 and of about 40:1 (depending on the composition of the material to be etched). Typically, the selectivity for etching a conductive metal layer relative to a photoresist is within the range of about 2:1 and about 4:1. Thus, the photoresist layer must be about 0.25 to 0.5 times as thick as the conductive metal layer.
If an entire etch process is considered, the selectivity for etching film stack containing the conductive metal layer relative to the photoresist is only about 1:1. In other words, when a metal layer having a thickness of 5000 Å is to be etched, a photoresist mask having a thickness of at least 5000 Å is needed. The pattern transferred to the underlying metal layer will be affected if the photoresist mask is completely consumed during the etch process.
For many wet etch processes, selectivity for etching the conductive metal layer relative to the photoresist is very high; thus, the photoresist mask is not significantly affected. However, for dry etch processes, which are preferred from a process integration viewpoint, this is rarely the case. Thus, it is necessary to calculate the etch selectivities that a particular application will require, and only the masking material which meets the selectivity requirements of a dry etch process will be chosen.
From the standpoint of etch resistance and impurities encroachment, a thicker photoresist is preferable. However, the use of a thicker photoresist layer will negatively affect the accuracy of transferring a pattern to an underlying metal layer. A minimal thickness of photoresist is preferable to assure the best pattern transfer. Typically, the thickness of a conventional photoresist mask falls within the range of a few thousand Angstroms to 2 microns.
Mid-ultraviolet (UV) and deep UV technology offer a significant improvement in resolution because shorter wavelengths are utilized. Alternative radiation sources, such as X-ray and electron beam, have also been investigated, in an attempt to increase the resolution of the transferred pattern to fit the reduced size requirements of the next generation of semiconductor devices. Conventional photoresist materials are not appropriate for use with the new radiation sources and, therefore, new materials for masking must be developed. Nevertheless, conventional organic-based photoresists imaged using a mercury arc lamp to transmit a near-UV light source are capable of producing patterns on semiconductor substrates with feature sizes as small as about 0.8-1.5 &mgr;m. For submicron features, sidewall technology is typically used to further reduce the feature size.
As previously described, the selectivity of etching a conductive metal layer relative to a conventional photoresist material is less desired. In addition, the characteristics of interconnections are negatively affected when a thicker conductive line is required to further reduce the electrical interconnect delays. Resolution from photoresist to conductive layer remains a problem. Resolution is typically much better when a thinner photoresist layer is used.
Further, exposure of the organic-based photoresist mask during etching in a plasma reactor will result in deposition of polymer on adjacent film layers, thereby decreasing the etch rate of the conductive layer. Although controlled polymer deposition may be used during the anisotropic etching of interconnections, it is not desirable to have polymer deposition depend on the presence of a photoresist mask.
In summary, although all aspects of organic-based photoresist processing are well-understood, conventional organic-based photoresists provide minimal resolution for current device needs. Reliable integrated processes for the manufacture of tomorrow's smaller device feature sizes may not be practically achieved using conventional organic-based photoresist materials.
SUMMARY OF THE INVENTION
As described above, when conventional organic-based photoresists are used as masking layers in a plasma etching process for formation of conductive interconnections, the etch selectivity of the organic-based photoresists do not meet the resolution requirements of metal etching. As a result, the conductive interconnections formed have poor etch profiles. Further, polymeric species generated due to the exposure of the surface of the photoresist negatively affect the etching process. The method of the present invention utilizes an inorganic dielectric layer as a hard masking layer during metal etching.
A preferred embodiment of the invention relates to a method of pattern etching a stacked metal layer structure using an inorganic dielectric hard mask. A typical stacked metal layer structure for practicing the method of the invention includes, from top to bottom, an inorganic dielectric hard masking layer, an anti-reflection (ARC) layer, a conductive layer, a diffusion barrier layer, and a dielectric layer, all deposited on a surface of a silicon substrate. The dielectric hard masking layer preferably comprises a material selected from the group consisting of silicon dioxide, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, and silicon nitride. The ARC layer preferably comprises titanium nitride or silicon oxynitride. The conductive lay
Ting Chris
Yu Janet
Applied Materials Inc.
Bach Joseph
Bean Kathi
Church Shirley L.
Utech Benjamin L.
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