Methods of manufacturing integrated circuit devices in which...

Details Methods of manufacturing integrated circuit devices in which... Methods of manufacturing integrated circuit devices in which...

2001-11-29

2002-08-13

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S623000, C438S626000, C438S780000

Reexamination Certificate

active

06432843

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-72089, filed Nov. 30, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit devices and manufacturing methods therefor and, more particularly, to insulation layers that may be used to fill space between integrated circuit patterns and manufacturing methods therefor.
BACKGROUND OF THE INVENTION
In general, integrated circuit devices have become more highly integrated and may have multilevel architectures and/or minute elements therein. In highly integrated devices, an aspect ratio of a contact hole or a via hole that connects an upper and a lower element may be relatively high. Moreover, step coverage of an insulation layer may vary between high-density patterns and low-density patterns and/or between upper patterns and lower patterns. An insulation layer that provides good step coverage for a lower pattern, however, may cause problems in patterning an upper interconnection or element. Thus, it may be desirable to reduce the step coverage of an insulation layer depending on the region of an integrated circuit device. For example, it is common in dynamic random access memory (DRAM) manufacturing to fill narrow grooves between gate lines and/or bit lines formed at a substrate with an interlayer insulation layer, and then to planarize a top side of the interlayer insulation layer.
One approach to reducing the step coverage of an insulation layer, is to form a layer of boro-phospho-silicate-glass (BPSG) and then reflow the BPSG layer at a temperature over 830° C. Unfortunately, in highly integrated circuit devices, transistors may have a critical dimension of 0.2 microns or less. The thermal treatments of the BPSG layer, may adversely affect such transistors.
Other materials and methods may be used to form insulation layers, such as tetra-ethyl-ortho-silicate (ozone-TEOS), undoped silicate glass (USG), and high-density plasma chemical vapor deposition (HDP-CVD). Such materials and methods, however, may exhibit a void or a seam when used in integrated circuit devices that follow a design rule of 0.2 microns or less.
For example, an HDP-CVD oxide film may be used to fill a gap between bit lines in which the width of the gap is approximately 5000 Å and the height of the gap is approximately 10,000 Å. Unfortunately, a void may be formed in the HDP-CVD oxide film, which may cause cracks in subsequent processes. Thus, the reliability of an integrated circuit device may be degraded.
Another material that may be used in insulation layers is spin on glass (SOG). In general, SOG has relatively good gap filling properties, and may compensate for step coverage when thickly formed. After an integrated circuit device is coated with an SOG layer, densification and curing steps may be performed to eliminate unstable components from the SOG layer. For example, an SOG layer may be heated to a temperature between approximately 100° C. and 300° C. to remove a solvent component. The SOG layer may be further heated to a temperature of about 400° C. and/or may be annealed at a temperature of over 600° C. Unfortunately, SOG layers may be susceptible to cracks in thickly formed regions. Furthermore, chemical mechanical polishing is frequently performed to reduce the step coverage in SOG layers.
Even if an SOG layer is thermally treated, residual components may remain in the SOG layer that may degrade the characteristics of the SOG layer. For example, residual components such as organics, hydrics, and or other inorganic materials may cause problems relating to pollution of the device, the absorption of water, and the porousness of an SOG layer. In particular, residual components may remain in lower portions of gaps having high aspect ratios as the thermal treatment is generally more effective near the surface of an SOG layer.
If an SOG layer is left in a porous state due to the presence of residual components, then the porous regions of the SOG layer may etch more rapidly than other portions of the SOG layer. Moreover, stress differences due to thermal expansion may increase defect generation and may also reduce element reliability in an integrated circuit device.
For example, if a field effect transistor, such as a metal oxide semiconductor (MOS) transistor, is formed on a substrate with an inorganic SOG layer, such as hydro silsesquioxane (HSQ) or polysilazane, a porous layer may be formed in deep portions between the gate lines. The porous lower portion of the SOG layer may be exposed when forming a pad for a storage node contact or a bit line contact. Unfortunately, even small doses of etchant used in a cleaning step may erode the exposed lower SOG layer. As a result, a pipeline type bridge may be formed between adjacent pads through the exposed lower SOG layers, which may cause a short between electrical wires.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, an integrated circuit device is manufactured by forming a pattern on a substrate. The pattern may comprise two or more mesa regions. The pattern and the substrate are coated with a spin on glass layer and then the spin on glass layer is dissolved so that the spin on glass layer is recessed from upper surfaces of the mesa regions opposite the substrate.
In other embodiments, an insulation layer is deposited on the spin on glass layer between the mesa regions to form a composite insulation layer. The second insulation layer may comprise SiO
2
, SiN, and/or SiON. The spin on glass layer may comprise polysilazane, hydro silsesquioxane, silicate, and/or methyl silsesquioxane. Advantageously, the composite insulation layer may resist the formation of voids when applied in gaps having a high aspect ratio.
In still other embodiments, the spin on glass layer may comprise hydro silsesquioxane, and tetramethyl ammonium hydroxide may be used to dissolve the spin on glass layer. In other embodiments, the spin on glass layer may comprise methyl silsesquioxane, and a fluoride base semi aquose solution mixed with one or more of dimethyl acetate, fluoride ammonium, and the like may be used to dissolve the spin on glass layer. Alternatively, a fluoride base semi aquose solution mixed with one or more of dyglicol amin, hydroxyl amin, cathecole mono ethanol amin, and the like may be used to dissolve the spin on glass layer.
In further embodiments, a mask, such as photoresist, is formed on the spin on glass layer on a region adjacent the pattern before dissolving the spin on glass layer. The mask may then be removed after dissolving the spin on glass layer.
In still further embodiments, an integrated circuit device is manufactured by forming a pattern on a substrate. The pattern may comprise two or more mesa regions. The pattern and the substrate are coated with a spin on glass layer and then a solvent is removed from the spin on glass layer. The solvent may be removed by heating the spin on glass layer at a temperature in a range of about 50° C. to about 400° C.


REFERENCES:
patent: 6117798 (2000-09-01), Fang et al.
patent: 6146990 (2000-11-01), Sung et al.
patent: 6150274 (2000-11-01), Liou et al.
patent: 6214749 (2001-04-01), Watanabe et al.
patent: 6274515 (2001-08-01), Hughes et al.
patent: 6346473 (2002-02-01), Chang et al.

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