Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-01-23
2002-04-09
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S049130, C365S189050, C365S230080
Reexamination Certificate
active
06370073
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to semiconductor memories, especially dynamic random access memory (DRAM). In particular, the present invention relates to a method and apparatus of handling refresh operations in a semiconductor memory such that the refresh operations do not interfere with external access operations.
DISCUSSION OF RELATED ART
A conventional DRAM memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM cell, which consists of 4 to 6 transistors. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each refresh operation of a DRAM cell consumes memory bandwidth. For example, the cycle time of a 200 MHz DRAM array is 5 nsec. In this DRAM array, each external access takes 5 nsec, and each refresh access takes at least 5 nsec. Because an external access and a refresh access can be initiated at the same time, the DRAM array must be able to handle both within the allowable access cycle time so as to prevent the refresh access from interfering with the external access. This limits the minimum external access cycle time to be no less than 10 nsec, with 5 nsec for handling the external access and 5 nsec for handling the refresh access. This is true even though the refresh accesses are performed, on average, at a frequency of less than 100 KHz. As a result, the maximum accessing frequency of the DRAM array must be less than or equal to 100 MHz. Thus, a 200 MHz DRAM memory array is required to create a device capable of operating at 100 MHz. This is simply not economical.
Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device has required an external signal to control refresh operations. (See, 131,072-Word by 8-Bit CMOS Pseudo Static RAM, Toshiba Integrated Circuit Technical Data (1996).) Moreover, external accesses to this DRAM device are delayed during the memory refresh operations. As a result, the refresh operations are not transparent and the resulting DRAM device cannot be fully compatible with an SRAM device.
In another prior art scheme, a high-speed SRAM cache is used with a relatively slow DRAM array to speed up the average access time of the memory device. (See, U.S. Pat. No. 5,559,750 by Katsumi Dosaka et al, and “Data Sheet of 16 Mbit Enhanced SDRAM Family 4M×4, 2M×8, 1M×16” by Enhanced Memory Systems Inc., 1997.) The actual access time of the device varies depending on the cache hit rate. Circuitry is provided to refresh the DRAM cells. However, the refresh operation is not transparent to external accesses. That is, the refresh operations affect the memory access time. Consequently, the device cannot meet the requirement of total deterministic random access time.
Other prior art schemes use multi-banking to reduce the average access time of a DRAM device. Examples of multi-banking schemes are described in “Data sheet, MD904 To MD920, Multi-bank DRAM (MDRAM) 128K×32 to 656K×32” by MoSys Inc., 1996, and in “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's” by Kazushige Ayukawa et al, IEEE JSSC, vol. 33, No. 5, May 1998, pp. 800-806. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle.
Another prior art scheme uses a read buffer and a write buffer to take advantage of the sequential or burst nature of an external access. An example of such a prior art scheme is described in U.S. Pat. No. 5,659,515, entitled “Semiconductor Memory Device Capable of Refresh Operation in Burst Mode” by R. Matsuo and T. Wada. In this scheme, a burst access allows a register to handle the sequential accesses of a transaction while the memory array is being refreshed. However, this scheme does not allow consecutive random accesses. For example, the memory cannot handle a random access per clock cycle.
Another prior art scheme that attempts to completely hide refresh operations in a DRAM cell includes the scheme described in U.S. Pat. No. 5,642,320, entitled “Self-Refreshable Dual Port Dynamic CAM Cell and Dynamic CAM Cell Array Refreshing Circuit”, by H. S. Jang. In this scheme, a second port is added to each of the dynamic memory cells so that refresh can be performed at one port while a normal access is carried out at the other port. The added port essentially doubles the access bandwidth of the memory cell, but at the expense of additional silicon area.
Accordingly, it would be desirable to have a memory device that utilizes area-efficient DRAM cells, and handles the refresh of the DRAM cells in a manner that is completely transparent to an accessing memory client external to the memory device. That is, it would be desirable for the refresh operations to be successfully performed without relying on unused external access time. Stated another way, it would be desirable to have a memory device that allows the use of DRAM cells or other refreshable memory cells for building SRAM compatible devices or other compatible memory devices that do not require refresh. It would further be desirable for the memory device to utilize a single read/write port, thereby minimizing power consumption and required layout area.
SUMMARY
Accordingly, the present embodiment provides a memory device or an embedded memory block that includes a plurality of memory cells which must be periodically refreshed in order to retain data values, and a memory controller for accessing and refreshing the memory cells. In one embodiment, the memory cells are DRAM cells. The memory controller controls the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any external access of the memory cells.
In one embodiment, the memory cells are arranged in a plurality of independently controlled, single-port memory banks. Thus, read, write and refresh operations are independently controlled within each memory bank. In the preferred embodiment, each bank contains 32 rows and 512 columns. Each of the memory banks is coupled in parallel to a write buffer, a read buffer and an I/O interface through a single read/write port. In one embodiment the read buffer and the write buffer each have the same configuration as the memory banks. In another embodiment, the read buffer and/or write buffer can be constructed using SRAM cells.
The memory device is refreshed using a multi-bank refresh scheme. A central refresh timer generates a refresh request signal, which is provided to the memory banks, the read buffer and the write buffer during every proper refresh period. The proper refresh period is set equal to or less than the required refresh period of one of the memory cells, divided by the number of rows in a memory bank. In one embodiment, the refresh request signal is broadcast to all the memory banks. In another embodiment, daisy-chained connections sequentially pass the refresh request signal to the memory banks, the read buffer and the write buffer in response to a clock signal. A central refresh address generator generates a refresh address, which is provided to all of the memory banks in parallel. The refresh address generator increments the refresh address each time the refresh request signal is asserted. When the refresh request signal is activated, a memory bank executes a refresh cycle if there is no access conflict. Otherwise, the refresh cycle is delayed until there is no access conflict.
The memory controller ensures that each memory bank, the read buffer and the write buffer are properly refreshed during the proper refresh period. More specifically, the memory controller (and the configuration of the memory device) ensures that each of the memory banks will have at least one idle cycle during the proper refresh period, even under worst case conditions. A refresh operation can be completed within one clock cycle. Thus, by providing at least one idle cycle during the proper refresh period, the memory banks can fulf
Bever Hoffman & Harms LLP
Dinh Son T.
Hoffman E. Eric
Monlithic System Technology, Inc.
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