Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-22
2002-06-04
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S646000
Reexamination Certificate
active
06399486
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention teaches a method of electrochemical copper deposition (ECD) in dual damascene trench and via with high pressure and special annealing conditions to solve the void, electrolyte trapping problems and other defects associated with the ECD technique.
(2) Description of Related Art
The electrochemical copper deposition (ECD) has been adopted as the “standard” fill process for copper metallization because of its larger grain size (good electromigration) and high deposition rates. However, the ECD process is a wet process and causes void formation in the via or trench. Also, the electrolyte can also be trapped in the voids causing reliability problems. The conventional method is to anneal the copper film under atmospheric pressures or less. However, the voids are not eliminated during these conventional annealing processes. Similar to aluminum annealing processes, a high pressure and temperature “force fill” method is taught by this invention, to improve copper reliability. The present invention teaches a method for forming an electrochemical copper deposition (ECD) via and trench by using special high pressure, 100 to 600 MPa, and temperature annealing 300 to 500° C.
As a background to the current invention, the damascene process is a “standard” method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
Sputter deposition has some advantages as a metal deposition technique because it can be used to deposit many conductive materials, at high deposition rates, with good uniformity and low cost of ownership. Conventional sputtering fill is poorer for deeper, narrower (high-aspect-ratio) features. In addition, fill is especially bad for corners of recesses, which have relatively small acceptance angles for flux, and for thick depositions, since the upper surface deposition can block incoming flux and produce a void in the recessed feature.
The fill factor by sputter deposition has been improved by collimating the sputtered flux. Typically, this is achieved by inserting between the target and substrate a collimator plate having an array of hexagonal cells.
Chemical vapor deposition (CVD) of W usually requires an underlying conductive barrier and “seed” layers to prevent consumption of substrate Si from reaction with WF
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at the contact level, and to promote distributed nucleation and low contact resistance. A layer of Ti is used since it provides good adhesion and low contact resistance. However, the Ti alone is not sufficient, because the F from the WF
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reacts with the Ti and produces a brittle, high-resistivity compound. However, the use of a TiN film between the Ti and W solves these problems by enhancing W nucleation while preventing the reaction of F with the Ti or any exposed Si. A W seed layer is then formed on the TiN.
After deposition, CMP is applied to complete the inlaid structure. In the CMP process, material is removed from the wafer through the combined effects of a polish pad and an abrasive slurry. The chemical dissolution of material is aided by a mechanical component which is useful in removing passivating surface layers. Chemical and mechanical selectivity's between materials are desired, since CMP must remove the excess metal without removing appreciable amounts of inlaid metal or reducing interconnect thickness.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
The dual-damascene process can be more difficult to fill and planarize than the single-damascene processing. Specifically, the metal films must now fill features having aspect ratios much greater than 1. This can be attained with CVD W, provided the adhesive liner covers the recessed surfaces. To obtain adequate liner coverage using collimated sputtered (PVD) Ti/TiN liners, a larger liner thickness must be applied, which is then difficult to polish away, without dishing (W dishing due to its easy removal by CMP). Furthermore, the conformal filling afforded by CVD W results in local recesses over the high-aspect-ratio dual-damascene features that contribute to dishing during polishing.
Another metal deposition has been adapted as a standard for copper metallization. This technique is electrochemical copper deposition (ECD). It is used for the large grain size (low electromigration) and high deposition rates achieved. The electrochemical copper deposition (ECD) still needs sputtering techniques, physical vapor deposition (PVD), to deposit thin barrier film (Ta, TaN) and a conductive “seed” layer of copper. However, the electrochemical copper deposition (ECD) process is a wet process. The process causes some void formation in the via and trench, as the copper is electroplated and grows from all sides onto the seed layer. In addition, the electrolyte is easily trapped in the voids. These deleterious effects with electrochemical copper deposition (ECD) usually cause reliability problems. The conventional method to solve these problems of voids and trapped electrolyte is to anneal the copper film under atmospheric pressure or less. However, the voids cannot be completely eliminated during these conventional annealing processes.
Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 5,891,804 (Havemann et al.) teaches a copper electrolysis process. In an embodiment, a sputtered metal layer is formed and is subjected to a metal reflow or extrusion process. The sputtered metal is by high density plasma (HDP) and is followed by temperatures of between 300 to 600° C. and high pressures. This process is a method of forming a conductor on an interlevel dielectric layer which is over an electronic microcircuit substrate, and the structure produced thereby. The method utilizes: forming an intralevel dielectric layer over the interlevel dielectric layer; forming a conductor groove in the intralevel dielectric layer exposing a portion of the interlevel dielectric layer; anisotropically depositing a selective deposition initiator onto the intralevel dielectric layer and onto the exposed portion of the interlevel dielectric layer; and selectively depositing conductor metal to fill the groove to at least half-full. The selective deposition initiator may selected from the group consisting of tungsten, titanium, palladium, platinum, copper, aluminum, and combinations thereof. In one embodiment, the selective deposition initiator is palladium, a
Chen Sheng-Hsiung
Tsai Ming-Hsing
Ackerman Stephen B.
Blum David S
Chaudhuri Olik
Saile George O.
Taiwan Semiconductor Manufacturing Company
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