Method of forming a transistor with a strained channel

Details Method of forming a transistor with a strained channel Method of forming a transistor with a strained channel

2002-02-07

2002-12-10

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S285000

Reexamination Certificate

active

06492216

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a semiconductor device comprised with a tensile or compressive strained channel region used for performance enhancement.
(2) Description of Prior Art
An attractive approach for improving the performance of a metal oxide semiconductor field effect transistor (MOSFET), or of a complimentary metal oxide semiconductor (CMOS), device is the introduction of strain induced band modification for mobility enhancement to increase drive current. A compressive strained channel, such as a silicon-germanium channel layer grown on silicon, has significant hole mobility enhancement. A tensile strained channel, such as a thin silicon channel layer grown on relaxed silicon-germanium, achieves significant electron and hole mobility enhancement. The most common method of introducing tensile strain in a silicon channel region is to epitaxially grow the silicon channel layer on a relaxed silicon-germanium (SiGe), layer or substrate. The ability to form a relaxed SiGe layer is paramount in obtaining an overlying, epitaxially grown, silicon layer under biaxial tensile strain, however the attainment of the relaxed SiGe layer can be costly and difficult to achieve.
This invention will describe a process for forming a tensile strained silicon or silicon-germanium channel without the use of an underlying, relaxed SiGe layer. The underlying concept is the introduction of an element with a smaller atomic size than that of silicon, into the silicon or silicon-germanium layer to be used for the channel region. An example of such an element is carbon. The channel layer may therefore be comprised of silicon, germanium, and carbon, and have a lattice constant smaller than that of the underlying silicon substrate. As a result the channel layer will be under biaxial tensile strain. The attainment of the silicon channel layer under biaxial strain, incorporated into a CMOS device, will compute to improved carrier transport properties and thus enhanced MOSFET or CMOS performance. Prior art such as: Kibbel et al, in U.S. Pat. No 6,313,016; Liaw et al, in U.S. Pat. No. 5,891,769; Kawakubo et al, in U.S. Pat. No. 6,165,837; Chu et al, in U.S. Pat. No. 5,906,951; Fitzgerald et al, in U.S. Pat. No. 6,291,321; and Leoues et al, in U.S. Pat. No. 5,659,187, all describe processes for forming strained layers formed on underlying SiGe layers. However none of the above prior arts describe the novel process described in this present invention in which a tensile strained silicon, or silicon-germanium layer is obtained via incorporation of an atom into the channel layer, so that the channel layer has a lattice constant smaller than the lattice constant of the substrate material, therefore avoiding the use of a relaxed SiGe layer, as an underlying layer during epitaxial growth of the tensile strained channel layer. In this invention the incorporation of an atom smaller than silicon, such as carbon, into the channel layer can be performed during the epitaxial growth of the channel layer, or during subsequent processing steps such as by ion implantation. An example is the growth of a SiGe channel layer and the implantation of carbon into the SiGe layer.
SUMMARY OF THE INVENTION
It is an object of the invention to form a channel region for a MOSFET device, via use of a semiconductor alloy layer characterized as being under biaxial tensile or compressive strain, depending on the amount of incorporation of an element with a smaller atomic size than that of silicon.
It is another object of this invention to epitaxially grow the semiconductor alloy layer featuring biaxial tensile strain on a single crystalline silicon substrate, with the semiconductor alloy layer comprised of silicon or silicon-germanium, and an element with an atomic size smaller than that of silicon, such as carbon, resulting in a Si
(1−y)
C
(y)
or Si
(1−x−y)
Ge
x
C
y
alloy layer.
It is yet another object of this invention to form a silicon capping layer on the underlying semiconductor alloy layer to provide the needed silicon for a silicon dioxide gate insulator layer, obtained via thermal oxidation procedures.
In accordance with the present invention a method used to fabricate a MOSFET device featuring a semiconductor alloy channel region under biaxial tensile or compressive strain, epitaxially grown on an underlying single crystalline silicon substrate, is described. A semiconductor alloy layer is epitaxially grown on an underlying silicon substrate, with the semiconductor alloy layer comprised with an element with an atomic size different from that of silicon. One such semiconductor alloy, silicon-germanium-carbon, is epitaxially grown on the underlying semiconductor substrate, exhibiting the biaxial tensile or compressive strain desired for the channel region. If the carbon concentration y, is low compared to that of Ge, ie, y<0.1x, the Si
(1−x−y)
Ge
x
C
y
layer exhibits compressive strain. If the carbon concentration y, is high compared to that of Ge, ie, y>0.1x, the Si
(1−x−y)
Ge
x
C
y
layer exhibits tensile strain. A silicon capping layer is next epitaxially grown on the silicon-germanium-carbon layer, followed by a thermal oxidation procedure resulting in growth of a gate insulator layer, with the oxidation procedure consuming a top portion of the silicon capping layer. Definition of a gate structure is followed by formation of a source/drain extension region in an area of semiconductor materials not covered by the gate structure. After formation of insulator spacers on the sides of the gate structure, a heavily doped source/drain region is formed in an area of the semiconductor materials not covered by the gate structure or by the insulator spacers. A rapid thermal anneal procedure is used to activate the dopants in the source/drain region using conditions designed not to disturb the strain in the channel region. Metal silicide regions are formed on the source/drain and gate structures with an option of removing the silicon-germanium-carbon alloy prior to the silicidization procedure, then forming the metal silicide layer on the heavily doped source/drain region located in the silicon substrate, thus avoiding silicidization involvement with germanium and carbon atoms, while a second option entailing formation of metal silicide on raised source/drain structures.


REFERENCES:
patent: 4885614 (1989-12-01), Furukawa et al.
patent: 5659187 (1997-08-01), Legoues et al.
patent: 5891769 (1999-04-01), Liaw et al.
patent: 5906951 (1999-05-01), Chu et al.
patent: 6165837 (2000-12-01), Kawakubo et al.
patent: 6190975 (2001-02-01), Kubo et al.
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6313016 (2001-11-01), Kibbel et al.
patent: 2002/0011617 (2002-01-01), Kubo et al.

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