Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2001-01-09
2002-10-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
Reexamination Certificate
active
06461904
ABSTRACT:
BACKGROUND
The present invention relates to transistor structures.
A notched gate transistor provides a number of advantages in a semiconductor device. Since the gate length is smaller at the interface of the gate with the gate oxide, the total capacitance of the gate is reduced. Furthermore, by offsetting the interface of the gate with the gate oxide, from the source/drain extension implant regions (SDZ), a greater SDZ implant dose may be incorporated into the SDZ.
Notched gates for a notched gate transistor are illustrated in FIG.
3
. The gates
8
are on a gate oxide layer
10
, which is itself on a silicon substrate
2
. The lower portions of the gates include notches, causing those parts of the gates that come into contact with the gate oxide smaller than the top of the gates. This structure may be formed by the method shown in
FIGS. 1 and 2
.
FIG. 1
illustrates a substrate
2
, with a gate oxide layer
10
on the substrate, and a polycrystalline silicon (poly) layer
6
on the gate oxide layer. A photoresist layer
4
is applied on the poly layer
6
, and patterned, to form the structure shown in FIG.
2
. The poly layer is then etched, using the photoresist layer as a mask, to form the gates, and switched to an isotropic overetch, just prior to completion, to form the notches in the gates.
The above method of forming a notched gate transistor has disadvantages: it is difficult to consistently control the formation of the notch in the gate; and it is difficult to form spacers in the notch area. It would be desirable to have a method of forming a notched gate transistor without these disadvantages.
BRIEF SUMMARY
In a first aspect, the present invention is a method of forming a semiconductor structure, including filling a trench in a first dielectric layer with a gate material. The first dielectric layer is on a semiconductor substrate, and spacers are in the trench.
In a second aspect, the present invention is a method of making a semiconductor structure, including patterning a first dielectric layer, on a semiconductor substrate, to form a trench in the dielectric layer; forming spacers in the trench; and filling the trench with a gate material.
REFERENCES:
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patent: 5231038 (1993-07-01), Yamaguchi et al.
patent: 6204133 (2001-03-01), Yu et al.
Wolf; Silicon Processing for the VLSI Era vol. 2: Process Integration, Sunset Beach, CA, 1990, pp. 370-373.*
Encyclopedia of Chemical Technology, 14, 677-709 (1995).
Krusin-Elbaum, L. et al., “Electrical Characterization of ZrN”,Mat. Res. Soc. Symp. Proc., 71, 351-356 (1986).
Long, W. et al., “Dual Material Gate Field Effect Transistor (DMGFET)”,IEDM, 549-552 (1997).
Maiti, B. et al., “Metal Gates for Advanced CMOS Technology”,SPIE, 3881, 46-57 (199).
Van Zant, Peter,Microchip Fabrication, McGraw Hill, 3rdedition, 491-529 (1997).
Jin Bo
Yang Chan-Lon
Cypress Semiconductor Corp.
Lattin Christopher
Sonnenschein Nath & Rosenthal
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