Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-04
2002-10-01
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S525000, C438S531000
Reexamination Certificate
active
06458666
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistor fabrication and more specifically to a novel process for achieving a spot-implant for use in forming the pocket region in a MOSFET transistor without the use of a photo mask.
BACKGROUND OF THE INVENTION
The threshold voltage of a MOSFET transistor is the voltage that must be applied between the gate electrode and the source electrode to switch the transistor on. This threshold voltage is determined by the gate oxide (dielectric) thickness, the transistor gate length, and the doping concentration in the silicon substrate region beneath the transistor gate. Because most integrated circuits have a fixed voltage supply, the control of the threshold voltage to very tight tolerances across the circuit is crucial to ensuring the proper operation of the circuit. As the transistor gate or channel length is reduced below about 0.4 microns the short channel effect begins to dominate the transistor threshold voltage. This short channel effect results in a threshold voltage that decreases with decreasing gate length. In order to compensate for the short channel effect, an additional implant is introduced during the transistor fabrication process to increase the doping concentration in the substrate beneath the edges of the transistor gate. This additional implant is typically known as a pocket or halo implant.
As illustrated in
FIG. 1
, the pocket implants
31
,
32
are performed after the transistor gate
30
and the gate dielectric
20
is formed. The pocket implants
31
and
32
are usually angled implants that result in formation of regions
33
and
34
. The pocket implants are angled to ensure that some of the implanted species end up under the transistor gate
30
. The only areas of regions
33
and
34
that are effective in reducing the short channel effect are the areas at or under the transistor gate (or gate)
30
. In addition to the angled pocket implants described above, zero tilt implants are also used to form pocket regions. In addition to pocket implants, drain and source extension implants are also performed at this time and result in the formation of the doped region
35
shown in FIG.
1
. Because both the pocket implants and the drain and source extension implants are blanket implants of opposite dopant types (i.e. n-type and p-type) counter doping effects will make each region less effective. In addition to the silicon substrate
10
, the gate
30
is also subjected to both implants. The counter doping effect of the pocket implant in the gate could begin to have a deleterious effect on transistor operation as the size of the transistors is reduced.
To reduce the above described deleterious effects on transistor performance, a method for forming pocket regions of doping next to the edge of the gate without counter doping the drain extension and source extension regions is required. Currently such methods or fabrication process involve the use of photo masks. In such a process, photoresist would be formed and patterned to expose the silicon substrate next to the gate before the pocket implant process. Photolithographic processes however are the most expensive steps in the fabrication of MOSFET transistors and such a process would be prohibitively expensive. In addition, the alignment of a photo mask to a transistor gate on the substrate is very difficult. A low cost method that does not involve the use of a photo mask is required.
SUMMARY OF THE INVENTION
The instant invention describes a method for forming a spot implant region in a semiconductor substrate. An embodiment of the instant invention comprises the steps of: providing a semiconductor substrate with a gate dielectric over said semiconductor substrate and a transistor gate over said gate dielectric; forming a masking film on said semiconductor substrate and said transistor gate with an opening adjacent to said transistor gate; and forming a spot implant region in said silicon substrate adjacent and adjacent to said transistor gate by implanting a first species through said opening in said masking film; the transistor gate comprises polycrystalline silicon; the first species is an element from the group consisting of arsenic, phosphorous, boron, germanium, antimony, carbon, indium, and boron containing compounds and the masking film is silicon nitride.
The main advantage of the instant invention is the formation of a small area (spot) implant without the use of a photo mask. In an embodiment of the instant invention, the small area implant can be used as a pocket region of a MOS transistor. This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings
REFERENCES:
patent: 4962054 (1990-10-01), Shikata
patent: 5641711 (1997-06-01), Cho
patent: 5783457 (1998-07-01), Hsu
patent: 6271095 (2001-08-01), Yu
patent: 6297104 (2001-10-01), Tyagi et al.
Wolf, “Silicon Processing for the VLSI Era”, 1986, vol. 1, pp. 321-323.
Brady III W. James
Chaudhari Chandra
McLarty Peter K.
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