Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-11-08
2002-12-31
Lee, Thomas (Department: 2785)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C370S509000, C370S520000
Reexamination Certificate
active
06502197
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to synchronizing circuits generally and, more particularly, to an architecture and method for synchronizing a transport and path overhead generator and a transport and path overhead extractor to a transport and path overhead processor.
BACKGROUND OF THE INVENTION
As shown in the block diagram of
FIG. 1
, a conventional circuit
10
comprises a transport overhead/path overhead generator
12
, a transport overhead/path overhead extractor
14
, and a path and transport overhead processor
16
. The path and transport overhead processor
16
receives or generates a relatively large set of data communications signals. The path and transport overhead processor
16
comprises a path overhead interface
18
, a transport overhead interface
20
, a path overhead interface
22
and a transport overhead interface
24
. The path overhead interface
18
comprises a number of signals TPOH, TPOHEN, TPOHCLK and TPOHFP, and receives or generates signals RPOH, RPOHCLK and RPOHFP. Transmit and receive path overhead pins (e.g., “TPOH” and “RPOH”) are for respectively transmitting data to and receiving data from the path and transport overhead processor
16
. The path overhead and transport processor
16
transmits and receives path overhead clocks (e.g., RPOHCLK and TPOHCLK), transport overhead clocks (e.g., TTOHCLK and RTOHCLK),
15
transport overhead enable signals (e.g., XTOHEN), and start of the payload indicators (e.g., TPOHFP). The path overhead enable pin (e.g., TPOHEN) for the path overhead generator
12
indicates whether or not the current path overhead bytes should be used.
In this methodology, a separate interface is provided for transport overhead communication. For the transmit side, a transmit path frame signal TPOHFP is asserted by the path and transport overhead processor
16
to synchronize the generator
12
and the processor
16
. Once the path overhead generator
12
detects an asserted signal on the TPOHFP pin, all the path overhead bytes serially shift out on the data pin TPOH. This serial shifting of the data is timed and/or controlled by a clock signal (e.g., TPOHCLK).
For the receive side, the path overhead processor
16
asserts a receive frame signal (e.g., RPOHFP) in order to indicate to the path overhead extractor
14
that the path overhead is ready log and is being presented on the data pin (e.g., RPOH). Data extraction operations are timed and/or controlled by a clock (e.g., RPOHCLK).
A significant disadvantage of this conventional methodology is the relatively high pin count resulting from the separate transport overhead interfaces
20
and
24
and the path overhead interfaces
18
and
22
. For multiple framer chips (e.g., having 2, 4 or more path overhead processors), separate interfaces will increase the pin count significantly. Another disadvantage of such a conventional approach is the need for two additional separate sets of shift registers for the receive side and two separate sets of shift registers for the transmit side.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.
Another aspect of the present invention concerns a method for synchronizing a path overhead generator or a path overhead extractor to a path overhead processor, comprising the steps of (A) synchronizing at least one transport overhead byte with a pulse on an external pin, (B) presenting the transport overhead byte to the overhead processor in a first row and (C) processing the transport overhead byte in a second row, where the second row follows the first row.
The objects, features and advantages of the present invention include (i) providing an architecture and method that may reduce the number of pins per interface without losing functionality, (ii) combining the separate path overhead and transport overhead interfaces into a single interface, and/or (iii) using the single, combined interface to communicate between a path and transport overhead processor and an overhead generator and/or an overhead extractor.
REFERENCES:
patent: 3763758 (1973-10-01), Manack et al.
patent: 5461622 (1995-10-01), Bleickardt et al.
patent: 6263443 (2001-07-01), Anderson et al.
patent: 6298038 (2001-10-01), Martin et al.
Practical Data Communications, by Roger L. Freeman, 1995, pp. 433-448. Overhead Serial Communication Scheme, U.S. Serial No. 09/435749, filed Nov. 8, 199.
Overhead Serial Communication Scheme, U.S. Ser. No. 09/435,749, filed Nov. 8, 1999.
Cypress Semiconductor Corp.
Lee Thomas
Maiorana P.C. Christopher P.
Suryawanshi Suresh K
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