Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-24
2002-10-29
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S697000, C438S756000, C438S757000, C438S275000, C438S279000
Reexamination Certificate
active
06472271
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a planarization method and, more particularly, to a planarization method of memory unit of a flash memory. The present invention can meet the requirement of high planarity of memory unit of a flash memory to avoid micro scratches.
BACKGROUND OF THE INVENTION
Along with the trend of miniaturization of electronic devices, the tolerance of defect size in IC chips becomes more stringent. For instance, for the design rule below 0.25 &mgr;m since 1998, the tolerance of defect size is 0.08 &mgr;m, but for the present design rule below 0.18 &mgr;m (2001 A.D.), the tolerance of defect size shrinks to 0.06 &mgr;m. Therefore, the requirement of planarity for each level in ICs increases. Additionally, under the development trend toward high integration of ICs, the planarity of each level in an IC directly affects the difficulty of manufacturing a multi-layer stacked architecture. Based on the above two reasons, high planarity of each level in ICs becomes an important factor of consideration in modern semiconductor process.
Recently, a kind of memory (called flash memory) developed by Intel Inc. has proceeded toward the direction of replacing the hard disk drive and acquired hot responses on the market. Now, it is the single semiconductor product growing fastest on the semiconductor market. The flash memory is a non-volatile memory. That is, the memory or data stored therein will not disappear due to interruption of supply of power. The structure of the flash memory is the same as that of the electrically erasable programmable read-only memory (EEPROM). Nevertheless, to save time and manufacturing cost, it performs the operation of memory erasing block by block instead of bit by bit.
The CMP (chemical mechanical polishing) method is a commonly used technique nowadays for the planarization of memory unit of a flash memory. Although the CMP technique has the advantage of global planarization, it is difficult to control the stop point, hence easily abrading the polysilicon. Therefore, a silicon nitride layer is usually deposited on the surface of the polysilicon for protection. However, when applying to the fabrication process having shallow trench isolations (STI), silicon nitride easily remains in recessed regions. Additionally, the CMP technique also has the drawback of easily generating micro scratches. For memory unit of a flash memory having the requirement of high planarity, the above three drawbacks will affect subsequent processes to deteriorate the data retention of devices because of leakage of charges.
Accordingly, the present invention aims to propose a planarization method of memory unit of a flash memory to resolve the above problems in the prior art.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide a planarization method of memory unit of a flash memory, wherein the etching technique is adopted to replace the prior art CMP technique so that the requirement of high planarity of memory unit of the flash memory can be assured, the fabrication process can be simplified, and the tolerance of the etching mask can be increased.
The secondary object of the present invention is to provide a planarization method of memory unit of a flash memory, wherein angular structures of silicon dioxide of larger thickness at both sides of the polysilicon thereof can increase the contact area of the polysilicon with the insulating dielectric layer and the control gate thereon so as to increase capacitance and quantity of charges and to help electric conduction, hence effectively enhancing the function of memory unit of the flash memory.
The present invention exploits the following steps to achieve the above objects. First, a semiconductor substrate is provided. A polysilicon layer, which is used as the polysilicon of peripheral circuit and the polysilicon floating gates, and a silicon nitride on the polysilicon layer are disposed on the substrate. A silicon dioxide layer is formed on the substrate. An etching process is then performed to separate the silicon dioxide layer on the silicon nitride from the silicon dioxide layer beside the silicon nitride. Next, a second silicon nitride is formed. Subsequently, the silicon nitride and the silicon dioxide on the polysilicon of peripheral circuit are removed by etching, but the memory unit is protected with photoresist. The silicon dioxide remained on the polysilicon of peripheral circuit is then removed by sideward etching. Finally, the silicon nitride and the silicon dioxide thereon are simultaneously stripped using hot phosphoric acid.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:
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patent: 5272117 (1993-12-01), Roth et al.
patent: 6004843 (1999-12-01), Huang
patent: 6207501 (2001-03-01), Hsieh et al.
patent: 6380584 (2002-04-01), Ogawa
patent: 6391718 (2002-05-01), Jeng
Deo Duy-Vu
Kunemund Robert
Macronix International Co. Ltd.
Rosenberg , Klein & Lee
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