Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1994-06-14
2002-08-13
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S227000, C438S232000
Reexamination Certificate
active
06432759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor circuit fabrication, and more particularly to control of substrate current density in MOS and CMOS devices.
2. Background of the Invention
Metal-oxide-semiconductor (MOS) transistor circuits arc often preferred over bipolar junction transistor circuits when low power and low current circuit operation is desired. In a representative MOS transistor that relies upon n type minority charge carriers, referred to as an NMOS transistor, two heavily doped n type regions are formed in a lightly doped p type substrate. The two n type regions (called source and drain) are spaced apart from one another by a distance of the order of one micron (&mgr;m ) or less. The substrate region between these two n type regions becomes a p type channel through which n type (electron) minority charge can flow between the source and drain when a voltage difference is imposed between the source and drain regions. A voltage-controlled gate is provided over the channel region to control the distribution of p type charges (holes) in the channel. Application of a voltage to the gate provides a means to control the rate of minority charge flow (electrons) between source and drain in the channel.
In a representative PMOS transistor, two heavily doped p type regions are formed in a lightly doped n type substrate, separated by a channel of length of the order of 1 &mgr;m or less. A voltage-controlled gate is provided over the channel region to control the rate of minority charge flow (holes) between the p type source and p type drain.
In complementary MOS (CMOS) technology, an NMOS transistor and a PMOS transistor are fabricated adjacent to each other on the same substrate, which may initially be lightly doped or undoped. First and second wells of n type and p type, respectively, are formed in the substrate. One or more PMOS transistors are formed in the n type well, and one or more NMOS transistors are formed in the p type well. PMOS and NMOS transistors are paired together to create a CMOS device characterized by a very low standby current consumption. Circuits made from CMOS devices therefore require less power and generate less heat than equivalent circuits designed with NMOS or PMOS devices alone. CMOS circuitry is well suited for battery powered systems where low power consumption is often a critical design factor, and for extremely dense VLSI and ULSI circuitry where it becomes important to minimize the heat generated by the circuitry.
As CMOS device features decrease to sub-micron dimensions, the reliability of both NMOS and PMOS transistors becomes a concern, but more particularly the NMOS transistors. This is because a decrease in gate oxide thickness and an increase in current drive increases the possibility of the injection of very energetic conduction band electrons into the gate oxide region of an NMOS transistor in a phenomenon known as the “hot electron effect”. A hot electron has energy much greater than the energy required to occupy an electron state in the conduction band of the material. Hot electrons may produce hole-electron pairs by impacting upon die lattice of die material, and may become trapped in the gate oxide, creating a permanent charge in die oxide layer.
A partial solution to the hot electron effect, known in the prior art, is the provision of a lightly doped drain (LDD) structure. With a lightly doped drain, the interface region between the drain and the channel of the transistor is doped more lightly than the drain itself. This reduces the energy of the electrons flowing into the drain, and reduces the hot electron effect. However, the LDD structure somewhat reduces the performance of the transistor and does not completely eliminate the hot electron effect.
Another problem encountered in the prior art is the lowering of the transistor's threshold voltage V
th
as the channel length of the transistor is shortened. A low threshold voltage can lead to leaky and otherwise defective transistors. As a general rule, the threshold voltage should be at least 0.5 or 0.6 volts to prevent leakage problems. Since the threshold voltage is inversely related to the energy of the ion implantation which creates the source and drain regions of the transistor, the trend is to lower the implant energy as the channel length decreases to maintain the threshold voltage at a reasonable level. Currently, for short channel MOS transistors, it is desirable to maintain the implant energy for the source and drain regions at 30 keV or less. Implant energies much above 30 keV were considered to produce an undesirably low threshold voltage in the transistors and, therefore, were undesirable.
The prior art does not disclose a method or structure for providing a controllable decrease in substrate current density near the gate structure to suppress the hot electron effect without substantially degrading the performance of the transistor. Preferably, any such decrease should be accomplished with at most a modest increase in complexity of the circuit fabrication process, and should preferably utilize materials and additives normally used in a circuit fabrication process.
SUMMARY OF THE INVENTION
These needs are met by the present invention, which provides a method and structure for reduced substrate current density in metal oxide semiconductor (MOS) devices by moving the high current channel center away from the gate structure and increasing the effective width of this channel. The method for manufacturing the improved MOS devices utilizes industry standard materials and equipment.
A method for fabricating a MOS device in accordance with the present invention includes the steps of: a) providing a channel region of a first conductivity type in a semiconductor substrate; b) providing a gate structure over the channel region; and c) implanting ions of a selected species of a second conductivity type, opposite the first conductivity type, in the substrate adjacent to tile channel region with an implant energy of at least 40 keV. This high energy implant creates a deep, wide channel which reduces substrate current density and which moves the substrate current away from the gate structure. These characteristics greatly reduce the hot electron effect and greatly increase the operational life of the transistor.
A transistor device in accordance with the present invention includes a semiconductor substrate, a channel region formed in the substrate, a gate structure formed over the channel region, a source region formed in the substrate on a first side of the channel region, a drain region formed in the substrate on a second side of the channel region, where the source region and the drain region have doping concentrations of no more than 5×10
18
cm
−3
, and each of these two regions has a position of maximum doping concentration within the substrate which lies at least 0.06 &mgr;m below the gate structure. The provision of deep source and drain regions results in a deep channel, reducing the hot electron effect.
The method and structure of the present invention provides a source-gate-drain semiconductor device having substantially reduced peak current density in a channel region underlying and spaced from the gate structure. This procedure may be repeated, with n type and p type material interchanged, to produce a CMOS device.
This preferred approach produces an MOS transistor with several highly desirable features. First, the device has reduced peak substrate current density in a channel region underlying and adjacent to the gate structure of the device, because the current is spread over a wider channel. This allows use of smaller transistor channel length. Second, the hot electron effect is greatly reduced. Third, the lifetime of such a transistor increases dramatically, by a multiplicative factor of the order of 20 or more in some situations, depending upon the implant ion kinetic energies used. Fourth, these features are obtained with little or no increase in complexity of the processing steps.
These and othe
Coleman William David
LSI Logic Corporation
Pham Long
LandOfFree
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