Non-volatile memory device

Details Non-volatile memory device Non-volatile memory device

2001-07-25

2002-11-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S158000, C365S171000, C365S185180

Reexamination Certificate

active

06477077

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile memory device, and more particularly to a non-volatile memory device in which a storage element is formed by a magnetoresistive element made of a ferromagnetic thin film.
2. Related Art
Among electrical rewritable non-volatile memory devices, a memory device in which a storage element is formed by a magnetoresistive element made of a ferromagnetic thin film is referred to as magnetic RAM or MRAM.
FIGS.
3
(
a
) and (
b
) show the structure and operation of the conventional MRAM device.
As shown in FIG.
3
(
a
), the conventional MRAM device consists of a magnetization fixing layer
12
made of an approximately 20 nm ferromagnetic film which is formed on a lower interconnect layer
11
, a data storage layer
14
made of a ferromagnetic film of approximately 20 nm and an insulation layer
13
having a thickness of approximately 1.5 nm which is interposed between the magnetization fixing layer
12
and the data storage layer
14
, and an upper interconnect layer
15
which is formed on the data storage layer
14
.
FIG.
3
(
b
) shows a reading operation in the memory cell shown in FIG.
3
(
a
).
In a memory device formed by a magnetic thin film in which the direction of magnetization of the fixed layer
12
is fixed, and the direction of magnetization of the data storage layer
14
changes depending upon the stored information, a storage operation is performed by detecting a difference in the tunnel current flowing between the lower interconnect layer
11
and the upper interconnect layer
15
. That is, between the conditions in which the magnetization directions of the fixed layer
12
and the data storage layer
14
are mutually parallel (corresponding to the data “0”) and anti-parallel (corresponding to the data “1”), there is a change in the resistance value of the insulation film
13
of 10% to 40%, this being known as the tunnel magnetoresistive effect (TMR), which is used to perform storage. In actuality, an external magnetic field is used to change the magnetization direction of the data storage layer
14
so as to perform binary storage.
If the above-noted conditions are implemented, the readout of data can be done by applying a prescribed potential between the upper interconnect layer and the lower interconnect layer, so that a tunnel current flow from the lower interconnect layer
11
through the upper interconnect layer
15
, via the fixed layer
12
, the insulation layer
13
and the data storage layer
14
. That is, by means of the tunnel magnetoresistive effect, the resistance value changes depending upon whether the magnetization directions of two ferromagnetic layers sandwiching an insulation layer are parallel or anti-parallel, so that the reading of the stored information is performed by detecting the current change.
The above is the so-called tunnel magnetoresistive (TMR) effect, which is simplifies the formation of lead-out electrodes for guiding data to the outside in comparison to the giant magnetoresistive (GMR) effect of the past, this being an advantage in forming a high-density MRAM.
FIG.
4
(
a
) shows an actual MRAM, in which the memory cells shown in
FIG. 3
are arranged in an array.
In this MRAM, there are a plurality of lower interconnects serving as word lines, and a plurality of upper interconnects serving as bit lines arranged in a direction different from that of the word lines. The above-noted memory cells are located at the intersection points of this matrix. An arbitrary cell in the MRAM is selected by a word line and a bit line, and the tunnel current between the word line and the bit line is detected, so as to enable the stored information to be extracted to the outside.
An example of this type of memory in the past is, for example, disclosed in Japanese Patent Publication (KOKAI) 2000-82791. In the configuration described in that publication as well, the change in the tunnel current in an MTJ (magnetic tunnel junction) element formed between a lower interconnect and an upper interconnect is detected so as to readout stored information.
In this manner, an MRAM using the TMR effect usually has a structure consisting of a magnetoresistive element with at least three layers, that is, two ferromagnetic thin films with an insulation film therebetween, the change in the magnitude of an external magnetic field being used to make the magnetization directions of the two ferromagnetic thin films either parallel or anti-parallel, which changes the tunnel electrical current in the insulation film, thereby enabling the storage of data “
1
” or data “
0
”.
FIG.
4
(
b
) shows a write operation in an actual MRAM having the memory cells of
FIG. 3
arranged in an array.
In the MRAM memory cells of the past, when writing data, write currents C
1
and C
2
are caused to flow in the selected word line (W
112
) and bit line (B
152
), respectively, and the magnetic fields induced in the area surrounding the interconnects (magnetic fields M
1
and M
2
) and the combined magnetic field M
12
are used to arrange the magnetic domains in the data storage layer within the memory cell in one direction.
To store information that is the opposite of the above, if the current direction of one of the selected word line (W
112
) and bit line (B
152
), for example, that of the bit line (B
152
) is reversed to the direction opposite that when information was stored as noted above, the direction of the magnetic field M
2
can be changed by 180 degrees. Because as a result the combined magnetic field M
12
is changed by 90 degrees, the direction of the magnetic domain in the data storage layer within the memory cell is forcibly reversed. In this manner, it is possible to establish the direction of the magnetic domain with respect to the direction of the magnetic domain of the fixed layer, in which the direction of the magnetic domain does not change by an external magnetic field.
In an MRAM memory cell of the past, when writing data, by causing a prescribed current to flow in the word line and bit line, the magnetic field induced in the area surrounding the interconnects is used to forcibly reverse the direction of the magnetic domain of the data storage layer in the memory cell, and a current of 10 mA to 20 mA (writing current) is usually required to make this forcible reversal of the direction of a magnetic domain.
In the technology for manufacturing semiconductor devices such as an MRAM, it is usual and common to use aluminum or copper for the word and bit lines, the electrical resistance of each material being approximately 100 m&OHgr;/□ for aluminum and approximately 40 m&OHgr;/□ for copper, respectively.
When using these materials, the potential drop in the interconnect by the writing current flowing therethrough is expressed for the case of a copper interconnect as follows. 40 m&OHgr;/□×(10 mA to 20 mA)×interconnect length ratio
In the above, the interconnect length ratio is the ratio of the interconnect length divided by the interconnect width. For example, in the case of an interconnect length ratio of 2000, the potential drop would be
40m&OHgr;/□×(10 mA to 20 mA)×2000=0.8 to 1.6 V
The above means that a maximum potential difference of 1.6 V will occur at both ends of the interconnects (word line and bit line) . For example, if one end is at the ground potential, unless the reverse end is made 1.6 V, the above-noted write current will not flow.
A problem which arises in this case is described below, with reference to
FIG. 5
of the accompanying drawings.
FIG. 5
is a schematic representation of a memory cell array in an MRAM.
In
FIG. 5
, W
1
to Wm are word lines of the array, and B
1
to Bn are bit lines of the array. C
11
is a memory cell provided at the intersection point between the first word line (W
1
) and the first bit line (B
1
), and in the same manner Cmn represents a memory cell provided at the intersection point between the m-th word line (Wm) and the n-th bit line (B

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