Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-10-31
2002-08-27
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S797000
Reexamination Certificate
active
06442727
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacture and, more particularly, to a method, circuit and apparatus for electrically writing indicia upon and reading indicia from an integrated circuit (“die”) during production, test or programming of the die. The indicia is placed so that erroneous indicia can be ignored or corrected, so that the indicia remains highly reliable as to a die which it uniquely identifies from among numerous, similarly manufactured and configured die according to how, when and where the die was manufactured, tested or programmed, etc.
2. Description of the Related Art
An integrated circuit is often referred to as a die or chip. Those terms are henceforth interchangeably used. A die may contain several thousand active and passive devices, formed on a monolithic substrate. Those devices can be interconnected to form an overall circuit. Active devices include transistors, whereas passive devices include resistors and capacitors, for example.
Active and passive devices can be coupled to form one or more memory elements arranged across a die. A popular memory device is one which can be electrically programmed after the die is manufactured. However, once the storage elements are programmed, they are preferably non-volatile. Present non-volatile storage elements include, for example, programmable read only memory (PROM), fuses and/or anti-fuses, etc. Examples of popular PROMs include EPROMs, EEPROMs or flash EPROMs.
A problem common to non-volatile storage elements is their tendency to lose or gain charge after they are programmed or erased. Thus, a programmed element may lose its programmed state or a non-programmed element may gain program status. Charge loss or gain may occur when the die is stressed either through electrical interactions or heat cycles applied thereto.
Methods used to test charge loss or gain involve programming a pattern into the array of storage elements, stressing the die and thereafter reading bits within the array. If the location of read bits corresponds to the programmed locations, then charge loss or gain appears not to have occurred, at least for the bits associated with that test pattern.
In most instances, a manufacturer will test the non-volatile storage elements while the die is associated with a wafer. The manufacturer may perform more extensive tests after the previously tested (i.e., “probed”), viable die are packaged. Both the probe test and the packaged die test can be performed at numerous temperatures, and the storage elements can be programmed with multiple patterns to check for charge gain or loss. However, testing the storage elements implies that those elements can be programmed and re-programmed in multiple ways. A problem exists if a portion of the storage elements can only be programmed with a unique bit pattern existing prior to the probe test. If a pattern is applied to the previously programmed bits, the uniqueness of those bits will be lost.
It would be desirable to utilize a set of storage locations which receive information unique to the die on which they are programmed. Attributing information as to the manufacture, test, and programmability of a die into that set of storage devices would be beneficial in tracing performance history to the parameters by which that die was produced, tested, and programmed. The desirous technique of electrically programming non-volatile storage elements of each and every die with a unique bit pattern would prove valuable to an integrated circuit manufacturer who desires traceability of a die to how that die was manufactured, when it was manufactured, how it was tested, results from those tests, testers used, where the die was drawn from a wafer, from a wafer lot, how the die was processed, processing equipment used, programming equipment used, the method/equipment used, etc.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an electrically programmable integrated circuit, die or chip. By design, the present die is programmed solely by the manufacturer, or by an end user given instructions by the manufacturer. A unique set of product engineering (“PE”) bits is programmed by the manufacturer into storage elements within an address space which the customer or end user will not access during normal operation of the die.
The address space reserved for the PE bits is designed to access one or more storage locations embodied within the die. Each storage location comprises non-volatile storage elements, which, when programed, hopefully maintain their programmed value. Viability of the programmed storage locations reserved for PE bits cannot be tested since the PE bits can be written prior to the probe test—i.e., the PE bits may be programmed as early as wafer engineering test immediately subsequent to wafer manufacture. If charge loss or charge gain is encountered in programmed storage elements containing the uniquely programmed PE bits, then redundancy and/or error correction appears as a better alternative than applying a test pattern.
According to a first embodiment, product engineering bits are programmed or written to at least three storage locations spaced from each other across the die. The PE bits are identically placed in each storage location by accessing the reserved address space which will not be accessed during normal operation of the integrated circuit. If the PE bits subsequently read from each storage location are dissimilar, the correct or valid set of PE bits is determined by comparing each and every bit across respective storage locations. If a set of PE bits within one location is read identical to PE bits in another location, then it is determined those PE bits are the originally stored PE bit values provided, of course, that two storage locations represent a majority of locations reserved for the PE bits.
Adding redundant storage locations spaced distances from each other across the die ensures that if manufacturing defects are localized in one area, defects in that area will adversely affect only one storage location—i.e., only a minority of storage locations. The number of storage locations chosen is at least three so that a comparison of PE bits read from those locations will yield a majority concurrence. It is recognized, however, that more than three storage locations may be used if it is determined that die fabrication might consistently produce two defective storage locations. In that instance, four or more storage locations may be formed across the die. More preferably, an odd number of storage locations, beginning with three and incrementing by two is desired.
According to another embodiment, rather than adding redundant storage locations, additional bits and/or words can be added to a single storage location to essentially achieve the same result while utilizing less silicon surface area. In this embodiment, programming additional bits and reading those bits along with the PE bits allows detection of errors in the PE bits. If a sufficient number of extra bits are added, correction of defective PE bit errors is achieved. The additional bits can be considered parity bits, checksum bits or hamming-coded bits, generally recognized for their error detection/correction capabilities.
The benefit of adding redundant storage locations or error detection/correction bits proves beneficial in ensuring uniquely programmed PE bits remain as such. The PE bits and, more specifically, the storage locations which receive the PE bits can therefore be programmed early in the manufacturing cycle, and the unique values of the programmed PE bits (regardless of their validity) remain throughout the time in which test patterns are introduced into the storage locations exclusive of those which contain the PE bits. Testing the PE bit storage location when the normal memory array is tested would, unfortunately, wipe out manufacturing or previous test information stored therein. Accordingly, it is imperative that the present redundancy mechanism be used, and that redundancy be applied thr
Conley & Rose & Tayon P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Ton David
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