Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-31
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S271000, C438S272000, C257S330000
Reexamination Certificate
active
06376315
ABSTRACT:
BACKGROUND OF THE INVENTION
Metal oxide semiconductor field effect transistor (MOSFET) devices using trench gates provide low turn-on resistance and are often used for low power applications. In a trench MOSFET device, the channels are arranged in a vertical manner, instead of horizontally as in most planar configurations.
FIG. 1
shows a cross-sectional view of a conventional trenched gate MOSFET device having a unit cell designated by reference numeral
2
. The MOSFET cell
2
includes a trench
4
filled with conductive material
6
separated from the silicon regions
8
by a thin layer of insulating material
10
. A body region
12
is diffused in an epitaxial layer
18
, and a source region
14
is in turn diffused in the body region
12
. Due to the use of these two diffusion steps, a transistor of this type is frequently referred to as a double-diffused metal oxide semiconductor field effect transistor with trench gating or, in brief, a “trench DMOS”.
As arranged, the conductive and insulating materials
6
and
10
in the trench
4
form the gate
15
and gate oxide layer
16
, respectively, of the trench DMOS. In addition, the depth L measured from the source
14
to the epitaxial layer
18
constitutes the channel length L of the trench DMOS cell
2
. The epitaxial layer
18
is a part of the drain
20
of the trench DMOS cell
2
.
When a potential difference is applied across the body
12
and the gate
15
, charges are capacitively induced within the body region
12
adjacent to the gate oxide layer
16
, resulting in the formation of the channel
21
of the trench DMOS cell
2
. When another potential difference is applied across the source
14
and the drain
20
, a current flows from the source
14
to the drain
20
through the channel
21
, and the trench DMOS
2
is said to be in the power-on state.
The conventional trench DMOS device described above has an inherently high threshold voltage. Referring to
FIG. 1
, the threshold voltage is defined as the minimal potential difference between the gate
15
and the body
12
that is required to create the channel
21
in the body region
12
. The threshold voltage is dependent upon a variety of factors, including the thickness of the gate oxide
16
and the impurity concentration of the body region
12
.
Frequently, the thickness of the gate oxide
16
is reduced to lower the threshold voltage. Unfortunately, this approach seriously undercuts the final production yield as well as the reliability of the trench DMOS. For example, as can be seen from
FIG. 1
, the thinner the gate oxide layer
16
, the higher the probability of the conductive material
6
short-circuiting the semiconductor regions
8
through a defect in the gate oxide layer
16
. Moreover, a decrease in oxide thickness increases the gate charge, reducing switching speed.
Another way to reduce the threshold voltage is to lower the impurity concentration of the body region
12
.
FIG. 2
shows the diffusion profile of a trench DMOS cell. The x-axis of
FIG. 2
represents the distance measured from the planar surface
22
and into the source
14
, body region
12
and drain region
20
of FIG.
1
. For example, the source region
14
is located between x=0 to x=x
js
. Similarly, the body region
12
is positioned between x=x
js
and X=x
jb
. The drain region
20
begins at x=x
jb
and continues to the right-hand edge of FIG.
2
. The y-axis of
FIG. 2
corresponds to the impurity concentration (absolute value) of the various regions.
During normal operation, the drain region
20
and the body region
12
are reverse biased. Consequently, a depletion layer is formed, characterized by a depletion region
24
with a depletion width W as shown in FIG.
1
. As is well known in the art, the lighter the impurity concentration of a region, the wider the depletion width W extending into that region. Referring back to
FIG. 1
, if the body region
12
is too lightly doped, the depletion layer
24
may reach the source region
14
during operation, resulting in an undesirable effect called “punch-through”. During punch-through, current flows directly from the source
14
to the drain
20
without passing through the channel
21
, and breakdown ensues.
Referring again to
FIG. 2
, the hatched area underneath the impurity curve
30
from x=x
js
to x=x
jb
corresponds to the total charge stored in the body region
12
. The threshold voltage of the trench DMOS cell
2
can be lowered by reducing the impurity concentration of the body region
12
, as is graphically shown by the lowered curve
26
(shown with a dashed line in FIG.
2
). The lowering of the impurity concentration in the body region
12
, however, results in a widening of the depletion layer
24
and increases the possibility punch-through in the trench DMOS
2
as described above.
There have also been attempts to diffuse the source region
14
to a deeper depth, as shown in
FIG. 2
by another dashed line curve
28
, intersecting with the body impurity diffusion curve
30
to form a new source junction. As with reducing impurity concentration in the body region
12
, the purpose is to reduce the total charge stored in the body region
12
and thus reduce threshold voltage. However, punch-through is made more likely in this scenario, because the distance traveled by the depletion layer
24
before reaching the source region
14
is reduced.
Yet another approach is presented in U.S. Pat. No. 5,907,776. In this patent, the conventional dopant profile for the body region, illustrated by dashed line
30
in
FIG. 3
, is altered. The y-axis in
FIG. 3
, which is analogous to that of
FIG. 2
, corresponds to the absolute impurity concentration of the various regions of the semiconductor structure
2
. In
FIG. 3
, the impurity concentrations of the source region
14
, the body region
12
and the drain region
20
are represented by the curves
64
,
66
and
68
, respectively. Again, the source region
14
is located between the planar surface (x=0) and x=x
js
, the body region
12
is positioned between x=x
js
and x=x
jb
, and the drain region
20
begins at x=x
jb
. It should be noted that in
FIG. 3
, the excess impurity concentration for the body impurity curve
66
adjacent source boundary x=x
js
is truncated relative to the conventional body impurity curve
30
, which is shown in dashed lines. The leveling of the impurity profile for curve
66
adjacent to the source/body boundary x=x
js
serves several functions. First, the threshold voltage is substantially reduced due to the reduced impurity concentration (and hence reduced total charge) in the body region
12
. Moreover, the reduction in charge is remote from the body/drain boundary x=x
jb
where the depletion region
24
originates and extends. As a result, there is practically no compromise in the impurity concentration in the bulk of the body region
12
as far as the depletion layer is concerned, and the reduction in impurity concentration has little effect on punch-through.
U.S. Pat. No. 5,907,776 teaches that the truncated body diffusion curve
66
of
FIG. 3
is created by body region compensation, preferably involving successive implantation steps. See, e.g., col. 5, line 48 to col. 6, line 13 and col. 7, lines 39-56. A P-type material such as boron is preferred, because it requires less implant energy than other N-type counterparts. Compensation with a P-type impurity means that that body region must be N-type and hence the transistor must be of the P-N-P variety. An N-P-N structure (i.e., an N-channel device), however, is frequently more desirable than a P-N-P structure (i.e., a P-channel device), because such structures have better current capability due to higher electron mobility. Compensation of a P-type body region with an N-type dopant, however, requires one or more high-energy implantation steps. For example, referring to FIG. 6 of U.S. Pat. No. 5,907,776, a penetration distance of 0.3 microns (which is exemplified in this
Hshieh Fwu-Iuan
So Koon Chong
Blum David S
Bonham, Esq. David B.
Bowers Charles
General Semiconductor Inc.
Mayer Fortkort & Williams PC
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