Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
1998-03-03
2002-08-27
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S422000, C438S425000, C438S427000, C438S439000
Reexamination Certificate
active
06440819
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to local oxidation of silicon (LOCOS) processes and more particularly to differential field oxide growth on a single wafer.
2. Description of Related Art
Generally, in integrated circuit devices, active devices are formed on a semiconductor substrate. In integrated circuits such as memories, programmable logic devices (PLDs), and other integrated circuits, active devices must be electrically isolated from each other. One way to isolate the devices is to grow a field oxide region between devices, as shown in
FIG. 1
, typically through a local oxidation of silicon (LOCOS) process.
LOCOS processes typically begin with a silicon substrate upon which is grown a thin pad oxide (typically 100 Å-500 Å). A nitride (Si
x
N
y
) layer is deposited over the pad oxide. The nitride layer is patterned and parts are removed to form windows exposing the pad oxide. The resulting structure is shown in the cross-section of FIG.
2
A. Occasionally some or all of that portion of the pad oxide underlying the removed nitride portion is also removed exposing the substrate. The wafer is then exposed to an oxidizing ambient, either a wet or dry oxidant, and oxidation of the exposed substrate and pad oxide takes place. The result, shown in
FIG. 2B
, is a field oxide region that effectively isolates neighboring devices (transistors) from one another. Note that a pad oxide is not necessary for oxidation but is beneficial in relieving stress that occurs.
As shown in the cross-section of
FIG. 2B
, during the oxidation, the field oxide region not only grows vertically, up into the window formed by the patterned nitride and directly below the window into the substrate, but the oxidant also diffuses laterally, under the nitride. This lateral diffusion is known as encroachment (&Dgr;W) and forms an area in the field oxide known as the “bird's beak.” Encroachment is typically undesirable as it causes a larger field oxide area than is desired, thus decreasing packing density of devices per wafer. Because as field oxide thickness increases, encroachment also increases, one way to minimize encroachment is to use the minimum field oxide thickness required.
Memory devices can typically be divided into core and periphery regions, shown in the block diagram of FIG.
3
. The core region
110
contains specialized memory cells which are used solely for information storage, while the periphery region
100
contains various logic needed to make stored information accessible, making the two regions functionally distinct. Such center versus edge placement is typical, but not required, of memory cell structure.
Typically, during fabrication of memory cells, manufacturers grow field oxide regions of the same thickness in both the core and the periphery, usually approximately 4000 Å. However, due to device considerations, e.g., voltages, doping, and field thresholds, only an isolation region of approximately 2500 Å is needed between devices in the core compared with that required for the periphery. In addition, use of a smaller isolation region in the core decreases the amount of encroachment experienced in the core and would allow increased packing density for memory cells thereby allowing memory chips to either shrink in size or to increase storage capacity on the same size chip. Thus, it is desirable to grow field oxides of different thicknesses on a single substrate.
SUMMARY OF THE INVENTION
The present invention, roughly described, is directed toward a method for differential field oxide growth. It is desirable on some integrated circuits, and particularly memory devices, that the isolation, or field oxide, regions be of different thicknesses in the core area and the periphery area of the device. However, it is further desirable to be able to achieve differential field oxide growth using minimal patterning and growth steps.
The process used to achieve differential field oxide growth with minimal patterning and growth steps begins with a silicon substrate upon which is formed a pad oxide layer and a masking layer. Portions of the masking layer are removed to form “windows” in the masking layer. The window width in the core is smaller than the window width in the periphery. Use of the smaller window in the core takes advantage of the “field thinning effect.”
According to the “field thinning effect,” when the window width is smaller than a particular width specific to each oxidation process, oxidation will be significantly inhibited causing a smaller field oxide thickness to be grown than if the window width were larger. Thus, by patterning different sized windows in the core and periphery, different field oxide thicknesses can be grown in a single growth step.
A method in accordance with the invention further utilizes variable depth trenching. In accordance with one embodiment of the invention, a trench is formed in the substrate in alignment with each window prior to oxidation or oxide deposition. The trench formed in the wider windows (e.g., windows in the periphery region) is formed deeper than that formed in the narrower windows (e.g., windows in the core region). Oxidation or oxide deposition is then performed resulting in field oxide regions of variable width and of optimized planarity.
One embodiment of the invention forms trenches of variable depth by first growing field oxide regions of variable thickness, again in accordance with the “field thinning effect” by use of variable width windows. The resulting oxide regions of variable thickness are removed, resulting in deeper trenches where the removed oxide region was thicker and shallow trenches where the removed oxide regions were thinner. In this manner, trench depth is “self-tuned” to the window width.
The process in accordance with the invention is advantageous in that it improves packing density of devices per wafer because smaller field oxide thicknesses will be used when larger field oxide thicknesses are not required. Moreover, a method in accordance with the invention results in the formation of nearly planar field oxide regions.
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Advanced Micro Devices , Inc.
Duong Khanh
Fliesler Dubb Meyer & Lovejoy LLP
Jr. Carl Whitehead
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